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This paper presents a regular layout fabric made of via-programmable MCML universal logic cells for structured ASIC applications and the associated design flow. The proposed structured ASIC fabric offers very high noise immunity due to the differential operation, as well as low production cost due to the via-programmable properties of the universal logic cell. Implementations of a number of circuits are presented and the area/speed performances are compared with classical CMOS implementation using a commercial standard cell library in 0.18 μm CMOS technology.
Giovanni De Micheli, Alessandro Tempia Calvino, Andrea Costamagna
Tobias Kippenberg, Johann Emmeram Riemensberger, Mikhail Churaev, Xinru Ji, Zihan Li, Terence Albert Emile Blésin, Chengli Wang, Junyin Zhang, Xi Wang, Chen Yang, Wil Kao, Alisa Davydova