High-power, Thermally-accessible Dissipative Kerr Soliton Generation

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Parylene to silicon nitride bonding for post-integration of high pressure microfluidics to CMOS devices

Martinus Adela Maria Gijs, Ata Tuna Ciftlik

High pressure-rated channels allow microfluidic assays to be performed on a smaller footprint while keeping the throughput, thanks to the higher enabled flow rates, opening perspectives for cost-effective integration of CMOS chips to microfluidics circuits ...

Royal Society of Chemistry2012

Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff

Yusuf Leblebici

In this paper, the impact of the wire grid size on the power-delay-area trade off of VLSI digital circuits with differential routing is analyzed. To this aim, the differential MOS current-mode logic (MCML) is adopted as reference logic style, and a complet ...

Elsevier2010

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS

Jürgen Brugger, Marc Antonius Friedrich van den Boogaart

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 μm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ...

2008

Ultra-thin nanograin polysilicon devices for hybrid CMOS-NANO integrated circuits

Serge Ecoffey

The aim of this research is to develop and to evaluate devices and circuits performances based on ultrathin nanograin polysilicon wire (polySiNW) dedicated to room temperature operated hybrid CMOS-"nano" integrated circuits. The proposed polySiNW device is ...

EPFL2007