OneFile: A Wait-free Persistent Transactional Memory

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The growing need for connected, smart and energy efficient devices requires them to provide both ultra-low standby power and relatively high computing capabilities when awoken. In this context, emerging resistive memory technologies (RRAM) appear as a prom ...

In-memory computing is an emerging non-von Neumann computing paradigm where certain computational tasks are performed in memory by exploiting the physical attributes of the memory devices. Memristive devices such as phase-change memory (PCM), where informa ...

Resistive switching memory technologies (RRAM) are seen by most of the scientific community as an enabler for Edge-level applications such as embedded deep Learning, AI or signal processing of audio and video signals. However, going beyond a "simple'' repl ...

While Resistive Random Access Memories (RRAM) are perceived nowadays as a promising solution for the future of computing, these technologies suffer from intrinsic variability regarding programming voltage, switching speed and achieved resistance values. Wr ...

Modern large-scale data platforms manage colossal amount of data, generated by the ever-increasing number of concurrent users. Geo-replicated and sharded key-value data stores play a central role when building such platforms. As the strongest consistency m ...

A plethora of optimized mutex lock algorithms have been designed over the past 25 years to mitigate performance bottlenecks related to critical sections and locks. Unfortunately, there is currently no broad study of the behavior of these optimized lock alg ...

Non-Volatile Memory offers the possibility of implementing high-performance, durable data structures. However, achieving performance comparable to well-designed data structures in non-persistent (transient) memory is difficult, primarily because of the cos ...

The revolution of information-technology owes to silicon-based complementary-metal-oxide (CMOS) technology. However, CMOS technology approaches its physical limitation hardening the further progress of memory devices as well as computing paradigm requiring ...

The need for running complex Machine Learning (ML) algorithms, such as Convolutional Neural Networks (CNNs), in edge devices, which are highly constrained in terms of computing power and energy, makes it important to execute such applications efficiently. ...

Energy efficiency remains a challenge for the design of non-volatile resistive memories (ReRAMs) arrays. This memory technology suffers from intrinsic variability in switching speed, programming voltages and resistance levels. The programming conditions of ...

Non-Volatile Memory (NVM) technologies exhibit 4× the read access latency of conventional DRAM. When the working set does not fit in the processor cache, this latency gap between DRAM and NVM leads to more than 2× runtime increase for queries dominated by ...

This paper investigates the problem of deriving a white box performance model of Hardware Transactional Memory (HTM) systems. The proposed model targets TSX, a popular implementation of HTM integrated in Intel processors starting with the Haswell family in ...

OneFile: A Wait-free Persistent Transactional Memory

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RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures

Accurate Emulation of Memristive Crossbar Arrays for In-Memory Computing

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems

Write Termination circuits for RRAM : A Holistic Approach From Technology to Application Considerations

Efficient Protocols for Enforcing Causal Consistency in Geo-Replicated Key-Value Data Stores

Lock-Unlock: Is That All? A Pragmatic Analysis of Locking in Software Systems

Fine-Grain Checkpointing with In-Cache-Line Logging

ReRAM From Material Study to CMOS Co-integration

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

Switching event detection and self-termination programming circuit for energy efficient ReRAM memory arrays

Bridging the Latency Gap between NVM and DRAM for Latency-bound Operations

An Analytical Model of Hardware Transactional Memory