Karan Pathak

Expertise System Architect 2023 - (Ex-IMEC)Performance estimation and Analysis. CPU Micro-architecture (BP, TLB Pref., Cache Pref., etc.) Full System Simulation (gem5, QEMU)BSP, BIOS, System FirmwaresProgramming Models for LLMs for CXL-CPU-GPU systems (HPC+AI)FPGA Prototyping (CHISEL to Bitstream), OS support, FS over Network, DMA in FPGAs Current Work CXLRAMSim v1.0 : Supporting CXL devices in Full System Simulator. CXLRAMSim v2.0: Extensions for CXL switch in FS SimulatorCXL-PNM: Exploring new programming models for CXL-PNM using CXLRAMSimCXL Memory Analytical Modeling based on real hardware (CXL cards) characterizationMicro-architectural Innovations for Mitigating CXL latency. Education Masters | Embedded Systems 2023 – 2023 TU Delft Bachelors | ECE 2016 – 2016 NIT Hamirpur Professionals experiences System Architect Creating Validated simulation infrastructure for performance estimation of RISC-V architectures.Enabling Full-System simulation and emulation capabilities with Linux and Zephyr RTOSFPGA based prototyping of Heterogenous Compute Systems involving accelerators and multi-core systems.Creating RISC-V debugging infrastructure for high-end FPGAs with HBMs.Memory backend simulators to study  different technologies and their impact on ML workloads.Charactersation of Chip-level Interconnect protocol on FPGA.Baremetal Firmware development (bootloaders, Hardware Performance Counters) for emulated and simulated systems. 2023–2024 IMEC ResearchCurrent Research Fields Micro-architectureArchitectural SimulatorsCXL Memory PoolingCXL SwitchAccelerating Simulation/Checkpointing Awards Justus van Effen Fellowship TU Delft 2022 Erasmus Mundus Fellowship EU 2021 EIT Digital Masters Fellowship EU 2021 Summa Cum Laude TU Delft 2023 Silver Medal NIT Hamirpur 2016 Merit Fellowship SJVNL SJVNL 2012