Publications by Siang-Yun Lee | EPFL Graph Search

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This article proposes a new logic synthesis and verification paradigm based on circuit simulation. In this paradigm, high quality, expressive simulation patterns are pregenerated to be reused in multiple runs of optimization and verification algorithms, re ...

Adiabatic superconducting devices are promising candidates to develop high-speed/low-power electronics. Advances in physical technology must be matched with a systematic development of comprehensive design and simulation tools to bring superconducting elec ...

Electronic devices play an irreplaceable role in our lives. With the tightening time to market, exploding demand for computing power, and continuous desire for smaller, faster, less energy-consuming, and lower-cost chips, computer-aided design for electron ...

It is envisaged that spintronic logic devices will ultimately be utilized in hybrid CMOS-spintronic systems where signal interconversion between magnetic and electrical domains via transducers takes place. This underscores the vital role of transducers in ...

Superconducting electronics provide us with cryogenic digital circuits that can rival established technologies in performance and energy consumption. Today, the lack of tools for the design of large-scale integrated superconducting circuits is a major obst ...

Adiabatic quantum-flux-parametron (AQFP) circuits are a family of superconducting electronic (SCE) circuits that have recently gained growing interest due to their low-energy consumption, and may serve as alternative technology to overcome the down-scaling ...

quantum-flux-parametron (AQFP) logic is a superconductor logic family whose energy efficiency approaches theoretical limits. Because AQFP logic gates depend on a polyphase excitation current to perform their computation, gate fanins must arrive at the appr ...

The majority-inverter graph (MIG) is a homogeneous logic network widely used in logic synthesis for majority-based emerging technologies. Many logic optimization algorithms have been proposed for MIGs, including rewriting, resubstitution, and graph mapping ...

Adiabatic quantum-flux parametron (AQFP) is an energy-efficient superconducting technology. Buffer and splitter (B/S) cells must be inserted to an AQFP circuit to meet the technology-imposed constraints on path balancing and fanout branching. These cells a ...

Logic resynthesis is the problem of finding a dependency function to re-express a given Boolean function in terms of a given set of divisor functions. In this paper, we study logic resynthesis of majority-based circuits, which is motivated by the increasin ...

The paper presents a novel DAG-aware Boolean rewriting algorithm for restructuring combinational logic before technology mapping. The algorithm, called window rewriting, repeatedly selects small parts of the logic and replaces them with more compact implem ...

Siang-Yun Lee

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A Simulation-Guided Paradigm for Logic Synthesis and Verification

Majority-based Design Flow for AQFP Superconducting Family

Contemporary Logic Synthesis: with an Application to AQFP Circuit Optimization

Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers

Technology-Aware Logic Synthesis for Superconducting Electronics

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits

Impact of Sequential Design on the Cost of Adiabatic Quantum-Flux Parametron Circuits

Late Breaking Results: Majority-inverter Graph Minimization by Design Space Exploration

Beyond Local Optimality of Buffer and Splitter Insertion for AQFP Circuits

External Don’t Cares in Logic Synthesis

Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization

Technology Mapping for Beyond-CMOS Circuitry with Unconventional Cost Functions

Cost-generic Resubstitution Algorithm with Customizable Cost Functions

Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition

Boolean Rewriting Strikes Back: Reconvergence- Driven Windowing meets Resynthesis

Customizable On-the-fly Design Space Exploration for Logic Optimization of Emerging Technologies

An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications