Publications by Lana Josipovic

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

High-level synthesis (HLS) is the process of automatically generating circuits out of high-level language descriptions. Previous research has shown that dynamically scheduled HLS through elastic circuit generation is successful at exploiting parallelism in ...

When applications have unpredictable memory accesses or irregular control flow, dataflow circuits overcome the limitations of statically scheduled high-level synthesis (HLS). If memory dependences cannot be determined at compile time, dataflow circuits rel ...

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...

The efficiency of spatial computing depends on the ability to achieve maximal parallelism. This necessitates memory interfaces that can correctly handle memory accesses that arrive in arbitrary order while still respecting data dependencies and ensuring ap ...

Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have been widely used to implement a myriad of applications from different domains. As a result of their low-level hardware reconfigurability, FPGAs have much faster d ...

With FPGAs facing broader application domains, the conversion of imperative languages into dataflow circuits has been recently revamped as a way to overcome the conservatism of statically scheduled high-level synthesis. Apart from the ability to extract pa ...

To achieve resource-efficient hardware designs, HLS tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed together with operation scheduling to ensure the best possible unit usage at ...

The ability of dataflow circuits to implement dynamic scheduling promises to overcome the conservatism of static scheduling techniques that high-level synthesis tools typically rely on. Yet, the same distributed control mechanism that allows dataflow circu ...

High-level synthesis tools, both commercial and academic, typically rely on static scheduling to produce high-throughput pipelines. However, in applications with unpredictable memory accesses or irregular control flow, these tools need to make pessimistic ...

Commercial high-level synthesis tools typically produce statically scheduled circuits. Yet, effective C-to-circuit conversion of arbitrary software applications calls for dataflow circuits, as they can handle efficiently variable latencies (e.g., caches) a ...

PGAs are highly versatile devices, but their backend compilation process is significantly time-consuming. DynaRapid has demonstrated the potential to drastically reduce compilation times to mere seconds by leveraging macro-component-based design hierarchie ...

Lana Josipovic

Chat with Graph Search

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

From C/C plus plus Code to High-Performance Dataflow Circuits

Unleashing Parallelism in Elastic Circuits with Faster Token Delivery

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

Combining Dynamic & Static Scheduling in High-level Synthesis

High-Level Synthesis of Dynamically Scheduled Circuits

An Out-of-Order Load-Store Queue for Spatial Computing

Synthesizing General-Purpose Code Into Dynamically Scheduled Circuits

Speculative Dataflow Circuits

Resource Sharing in Dataflow Circuits

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

Invited Tutorial Dynamatic: From C/C plus plus to Dynamically Scheduled Circuits

Buffer Placement and Sizing for High-Performance Dataflow Circuits

DRSA: Accelerating Macro Placement on Commercial FPGAs

Resource Sharing in Dataflow Circuits

Buffer Placement and Sizing for High-Performance Dataflow Circuits

Enriching C-based High-Level Synthesis with parallel pattern templates

Dynamically Scheduled High-level Synthesis

From C to elastic circuits