Publications by Adam Shmuel Teman

Related publications (27)

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Robert Giterman, Andrea Bonetti, Adam Shmuel Teman

Among the different types of dynamic random-access memories (DRAMs), gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power, and CMOS-compatible alternative to conventional static random-access memory (SRAM). GC-eDRAM achieves high memory density, as i ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

Andreas Peter Burg, Adam Shmuel Teman, Pascal Andreas Meinerzhagen, Robert Giterman

Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall sili ...

2013

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Andreas Peter Burg, Luca Benini, Adam Shmuel Teman, Pascal Andreas Meinerzhagen

Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of vendors throug ...

Association for Computing Machinery2016

Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection

Robert Giterman, Adam Shmuel Teman

A gain-cell embedded DRAM (GC-eDRAM) is an attractive logic-compatible alternative to the conventional static random access memory (SRAM) for the implementation of embedded memories, as it offers higher density, lower leakage, and two-ported operation. How ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Approximate Computing With Unreliable Dynamic Memories

Andreas Peter Burg, Robert Giterman, Georgios Karakonstantis, Adam Shmuel Teman, Shrikanth Ganapathy

Embedded memories account for a large fraction of the overall silicon area and power consumption in modern SoC(s). While embedded memories are typically realized with SRAM, alternative solutions, such as embedded dynamic memories (eDRAM), can provide highe ...

2015

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

The rise of data-intensive applications has resulted in an increasing demand for high-density and low-power on-chip embedded memories. Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible alternative to conventional static random access memory (SRAM) w ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

Andreas Peter Burg, Adam Shmuel Teman, Pascal Andreas Meinerzhagen, Robert Giterman

Logic compatible gain cell (GC) embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, non-ratioed operation, low static leakage, and 2-port functionality. However, traditional GC-eDRAM implementations require boosted c ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories

Andreas Peter Burg, Georgios Karakonstantis, Pascal Andreas Meinerzhagen, Robert Giterman, Adam Shmuel Teman

Current variation aware design methodologies, tuned for worst-case scenarios, are becoming increasingly pessimistic from the perspective of power and performance. A good example of such pessimism is setting the refresh rate of DRAMs according to the worst- ...

2015

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Nicholas Alexander Preyss

Clocking power, including both clock distribution and registers, has long been one of the primary factors in the total power consumption of many digital systems. One straightforward approach to reduce this power consumption is to apply dual-edge-triggered ...

Association for Computing Machinery2017

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Robert Giterman, Andrea Bonetti, Adam Shmuel Teman

Among the different types of DRAMs, gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power and CMOS-compatible alternative to conventional SRAM. GC-eDRAM achieves high memory density as it relies on a storage cell that can be implemented with as few as ...

IEEE2020

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Adam Shmuel Teman, Robert Giterman

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher pow ...

MDPI2024

A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET

Andreas Peter Burg, Robert Giterman, Adam Shmuel Teman

Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible embedded memory alternative to SRAM, offering higher density, lower leakage power consumption, and an inherent two-ported functionality. However, increased leakage currents and process variations und ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes

Andreas Peter Burg, Adam Shmuel Teman, Pascal Andreas Meinerzhagen, Robert Giterman

Gain-Cell embedded DRAM (GC-eDRAM) has recently been recognized as a possible alternative to traditional SRAM. While GC-eDRAM inherently provides high-density, low-leakage, low-voltage, and 2-ported operation, its limited retention time requires periodic, ...

IEEE2014

A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI

Andreas Peter Burg, Adam Shmuel Teman, Jeremy Hugues-Felix Constantin, Andrea Bonetti

The increasing impact of variability on near-threshold nanometer circuits calls for a tighter online monitoring and control of the available timing margins. Error-detection sequentials are widely used together with error-correction techniques to operate di ...

IEEE2018

Impact of body biasing on the retention time of gain-cell memories

Andreas Peter Burg, Adam Shmuel Teman, Pascal Andreas Meinerzhagen

Gain-cell-based embedded dynamic random-access memory (DRAMs) are a potential high-density alternative to mainstream static random-access memory (SRAM). However, the limited data retention time of these dynamic bitcells results in the need for power-consum ...

2013

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to conventional SRAM due to its high-density, low-leakage, and inherent two-ported functionality. However, its dynamic storage mechanism requires power-hungry refresh cycles to maintain data. ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design

Andreas Peter Burg, Adam Shmuel Teman, Pascal Andreas Meinerzhagen, Robert Giterman

Gain cell embedded DRAM (GC-eDRAM) is a high-density alternative to SRAM for ultra-low-power systems. However, due to its dynamic nature, GC-eDRAM requires power-hungry refresh cycles to ensure data retention. Traditional design approaches dictate configur ...

Ieee2016

Dynamic stability and noise margins of SRAM arrays in nanoscaled technologies

Adam Shmuel Teman

SRAM stability is one of the primary bottlenecks of current VLSI system design, and the unequivocal supply voltage scaling limiter. Static noise margin metrics have long been the de-facto standard for measuring this stability and estimating the yield of SR ...

IEEE2014

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Jeremy Hugues-Felix Constantin, Thomas Christoph Müller, Lorenz Flavio Schmid

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs

Adam Shmuel Teman

As memory density continues to grow in modern systems, accurate analysis of SRAM stability is increasingly important to ensure high yields. Traditional static noise margin metrics fail to capture the dynamic characteristics of SRAM behavior, leading to exp ...

Institute of Electrical and Electronics Engineers2015