Publications by Giovanni Ansaloni

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Compute memories are memory arrays augmented with dedicated logic to support arithmetic. They support the efficient execution of data-centric computing patterns, such as those characterizing Artificial Intelligence (AI) algorithms. These architectures can ...

Analog in-memory computing (AIMC) cores offers significant performance and energy benefits for neural network inference with respect to digital logic (e.g., CPUs). AIMCs accelerate matrix-vector multiplications, which dominate these applications’ run-time. ...

We present a methodology for identifying patients who have experienced Paroxysmal Atrial Fibrillation (PAF) among a given subject population. Our work is intended as an initial step towards the design of an unobtrusive portable system for concurrent detect ...

2.5D Systems-on-Package (SoPs) are composed by several chiplets placed on an interposer. They are becoming increasingly popular as they enable easy integration of electronic components in the same package and high fabrication yields. Nevertheless, they int ...

The energy e fficiency of digital architectures is tightly linked to the voltage level (Vdd) at which they operate. Aggressive voltage scaling is therefore mandatory when ultra-low power processing is required. Nonetheless, the lowest admissible Vdd is o e ...

Efficient deployment of resource-intensive transformers on edge devices necessitates cross-stack optimization. We thus study the interrelation between structured pruning and systolic acceleration, matching the size of pruned blocks with the systolic array ...

The growing popularity of edgeAI requires novel solutions to support the deployment of compute-intense algorithms in embedded devices. In this article, we advocate for a holistic approach, where application-level transformations are jointly conceived with ...

Coarse-grained reconfigurable arrays (CGRAs) are a promising class of architectures conjugating flexibility and efficiency. Devising effective methodologies to map applications onto CGRAs is a challenging task, due to their parallel execution paradigm and ...

High-level synthesis (HLS) frameworks allow to easily specify a large number of variants of the same hardware design by only acting on optimization directives. Nonetheless, the hardware synthesis of implementations for all possible combinations of directiv ...

Coarse-Grain Reconfigurable Arrays (CGRAs) represent emerging low-power architectures designed to accelerate Compute-Intensive Loops (CILs). The effectiveness of CGRAs in providing acceleration relies on the quality of mapping: how efficiently the CIL is c ...

In the last decade, improvements on technology scaling have enabled the design of a novel generation of wearable bio-sensing monitors. These smart Wireless Body Sensor Nodes (WBSNs) are able to acquire and process biological signals, such as electrocardiog ...

This multi-partner-project contribution introduces the midway results of the Horizon 2020 FVLLMONTI project. In this project we develop a new and ultra-efficient class of ANN accelerators, the neural network compute cube (N2C2), which is specifically desig ...

The growing popularity of edge computing has fostered the development of diverse solutions to support Artificial Intelligence (AI) in energy-constrained devices. Nonetheless, comparatively few efforts have focused on the resiliency exhibited by AI workload ...

Approximate logic synthesis techniques have become popular in error-resilient systems, where accuracy requirements can be traded for improved energy efficiency. Many of these techniques operate on a circuit by substituting or removing some of its portions ...

Flow Cell Arrays (FCA) technology employs microchannels filled with an electrolytic fluid to concurrently provide cooling and power generation to integrated circuits (ICs). This solution is particularly appealing for Three-Dimensional Multi-Processor Syste ...

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional o ...

Latest embedded bio-signal analysis applications, targeting low-power Wireless Body Sensor Nodes (WBSNs), present conflicting requirements. On one hand, bio-signal analysis applications are continuously increasing their demand for high computing capabiliti ...

The ever-increasing computational complexity and energy consumption of today's applications, such as Machine Learning (ML) algorithms, not only strain the capabilities of the underlying hardware but also significantly restrict their wide deployment at the ...

The increasing size of Convolutional Neural Networks (CNNs) and the high computational workload required for inference pose major challenges for their deployment on resource-constrained edge devices. In this paper, we address them by proposing a novel In-M ...

This paper presents the system-level architecture of novel ultra-low power wireless body sensor nodes (WBSNs) for real-time cardiac monitoring and analysis, and discusses the main design challenges of this new generation of medical devices. In particular, ...

Giovanni Ansaloni

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Overflow-free compute memories for edge AI acceleration

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

Risk Assessment of Atrial Fibrillation: a Failure Prediction Approach

REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal

An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery

Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems

A hardware/software co-design vision for deep learning at the edge

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays

DB4HLS: A Database of High-Level Synthesis Design Space Explorations

SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs

A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing

FVLLMONTI: The 3D Neural Network Compute Cube (N2C2) Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge

A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis

Thermal and Power-Aware Run-Time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

Hardware/Software Approach for Code Synchronization in Low-Power Multi-Core Sensor Nodes

An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs

Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing

Ultra-Low Power Design of Wearable Cardiac Monitoring Systems