Publications by Luca Gaetano Amarù

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The continuous downscaling of CMOS Field Effec ...

In recent years, Boolean methods in logic synthesis have been drawing the attention of EDA researchers due to the continuous push to advance quality of results. Boolean methods require high computational cost, as they rely on complete functional properties ...

The majority function (xyz) evaluates to true, if at least two of its Boolean inputs evaluate to true. The majority function has frequently been studied as a central primitive in logic synthesis applications for many decades. Knuth refers to the majority f ...

Reducing the number of AND gates plays a central role in many cryptography and security applications. We propose a logic synthesis algorithm and tool to minimize the number of AND gates in a logic network composed of AND, XOR, and inverter gates. Our appro ...

With the continuous push to improve Quality of Results (QoR) in EDA, Boolean methods in logic synthesis have been recently drawing the attention of researchers. Boolean methods achieve better QoR than algebraic methods but require higher computational cost ...

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this work, we consider double independent gate, vertically-stacked nanowire FETs with gate-all-around structures and typical diameter of 20-nm. These devices, which we hav ...

A representation of a Boolean function is canonical if, given a variable order, only one instance of the representation is possible for the function. A computation is canonical if the result depends only on the Boolean function and a variable order, and do ...

In this paper, we develop a new LUT-based optimization flow tailored for the synthesis of ASICs rather than FPGAs. We enhance LUT-mapping to consider the literal/AIG cost of LUT-nodes. We extend traditional Boolean methods to simplify and re-shape LUT-netw ...

Logic synthesis is a fundamental step in the realization of modern integrated circuits. It has traditionally been employed for the optimization of CMOS-based designs, as well as for emerging technologies and quantum computing. Recently, it found applicatio ...

We present a multi-level logic refactoring algorithm based on exclusive sum-of-product (ESOP) expressions. ESOP expressions are two-level logic representation forms, similar to sum of -product (SOP) expressions. However, ESOPs use EXOR instead of OR operat ...

Majority-inverter graphs (MIGs) are a multi-level logic representation of Boolean functions with remarkable algebraic and Boolean properties that enable efficient logic optimizations beyond the capabilities of conventional logic representations. In this pa ...

Luca Gaetano Amarù

Chat with Graph Search

New Data Structures and Algorithms for Logic Synthesis and Verification

Extending Boolean Methods for Scalable Logic Synthesis

Majority Logic Synthesis

Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications

Scalable Boolean Methods in a Modern Synthesis Flow

Nanowire systems: technology and design (invited paper)

Canonical Computation without Canonical Representation

LUT-Based Optimization For ASIC Design Flow

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks

Integrated ESOP Refactoring for Industrial Designs

Scalable Generic Logic Synthesis: One Approach to Rule Them All

Logic Optimization of Majority-Inverter Graphs