Publications by Jian Zhang | EPFL Graph Search

Related publications (21)

Top-Down Fabrication of Gate-All-Around Vertically-Stacked Silicon Nanowire FETs with Controllable Polarity

Yusuf Leblebici, Giovanni De Micheli, Michele De Marchi, Davide Sacchetto, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

Asthe currentMOSFET scaling trend is facing strong limitations, technologies exploiting novel degrees of freedom at physical and architecture level are promising candidates to enable the continuation of Moore's predictions. In this paper, we report on the ...

Institute of Electrical and Electronics Engineers2014

Pyridine-Based Lanthanide Complexes Combining MRI and NIR Luminescence Activities

Lothar Helm, Jian Zhang

A series of novel triazole derivative pyridine-based polyaminopolycarboxylate ligands has been synthesized for lanthanide complexation. This versatile platform of chelating agents combines advantageous properties for both magnetic resonance (MR) and optica ...

2012

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits

Giovanni De Micheli, Shashi Kanth Bobba, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon, Subhasish Mitra

The quest for technologies with superior device characteristics has showcased Carbon-Nanotube Field-Effect Transistors (CNFET) into limelight. In this work we present physical design techniques to improve the yield of CNFET circuits in the presence of Carb ...

Assoc Computing Machinery2014

Configurable Logic Gates Using Polarity Controlled Silicon Nanowire Gate-All-Around FETs

Yusuf Leblebici, Giovanni De Micheli, Michele De Marchi, Davide Sacchetto, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

This work demonstrates the first fabricated 4-transistor logic gates using polarity-configurable, gate-all- around silicon nanowire transistors. This technology enhances conventional CMOS functionality by adding the degree of free- dom of dynamic polarity ...

Institute of Electrical and Electronics Engineers2014

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors

Giovanni De Micheli, Jian Zhang, Luca Gaetano Amarù, Pierre-Emmanuel Julien Marc Gaillardon

This brief presents a novel power-gating technique for differential cascade voltage switch logic (DCVSL) based on double-gate (DG) controllable-polarity field-effect transistors (FETs). DG controllable-polarity FETs, commonly referred to as ambipolar trans ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs

Yusuf Leblebici, Giovanni De Micheli, Michele De Marchi, Davide Sacchetto, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

We fabricated and characterized ambipolar Silicon Nanowire (SiNW) FET transistors featuring two independent Gate-All-Around (GAA) electrodes and vertically stacked SiNW channels. One of the gate electrodes is exploited to dynamically select the polarity of ...

2012

Operation regimes and electrical transport of steep slope Schottky Si-FinFETS

Giovanni De Micheli, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

In the quest for energy efficient circuits, considerable focus has been given to steep slope and polarity-controllable devices, targeting low supply voltages and reduction of transistor count. The recently proposed concept of the three-independent gated Si ...

2017

Dual-threshold-voltage configurable circuits with three-independent gate silicon nanowire FETs

Giovanni De Micheli, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

We extend ambipolar silicon nanowire transistors by using three independent gates and show an efficient approach to implement dual-threshold-voltage configurable circuits. Polarity and threshold voltage of uncommitted devices are determined by applying dif ...

2013

A Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

Giovanni De Micheli, Hassan Ghasemzadeh Mohammadi, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

This paper deals with the effects of faults on circuits implemented with controllable-polarity transistors. We propose a new fault model that suits the characteristics of these devices, and report the results of a SPICE-based analysis of the effects of fau ...

2016

Multiple-Independent-Gate Field-Effect Transistors for High Computational Density and Low Power Consumption

Jian Zhang

Transistors are the fundamental elements in Integrated Circuits (IC). The development of transistors significantly improves the circuit performance. Numerous technology innovations have been adopted to maintain the continuous scaling down of transistors. W ...

EPFL2016

Polarity-Controllable Silicon Nanowire Transistors with Dual Threshold Voltages

Yusuf Leblebici, Giovanni De Micheli, Michele De Marchi, Davide Sacchetto, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

Gate-all-around (GAA) silicon nanowires enable an unprecedented electrostatic control on the semiconductor channel that can push device performance with continuous scaling. In modern electronic circuits, the control of the threshold voltage is essential fo ...

Institute of Electrical and Electronics Engineers2014

Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

Giovanni De Micheli, Jian Zhang, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon

Silicon nanowire transistors with Schottky-barrier contacts exhibit both n-type and p-type characteristics under different bias conditions. Polarity controllability of silicon nanowire transistors has been further demonstrated by using an additional polari ...

Institute of Electrical and Electronics Engineers2014

Towards Functionality-Enhanced Devices: Controlling the Modes of Operation in Three-Independent-Gate Transistors

Giovanni De Micheli, Michele De Marchi, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

In this paper, we introduce the different modes of operation achievable with Three-Independent-Gate Field-Effect Transistors (TIGFETs) and report results on fabricated devices including: (i) the dynamic reconfiguration of the device polarity; (ii) t ...

2015

Process/Design Co-optimization of Regular Logic Tiles for Double-Gate Silicon Nanowire Transistors

Yusuf Leblebici, Giovanni De Micheli, Shashi Kanth Bobba, Michele De Marchi, Davide Sacchetto, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

Ambipolar transistors with on-line configurability to n-type and p-type polarity are desirable for future integrated circuits. Regular logic tiles have been recognized as an efficient layout fabric for ambipolar devices. In this work, we present a process/ ...

2012

Electronic decoupling and templating of Co nanocluster arrays on the boron nitride nanomesh

Klaus Kern, Jian Zhang

Positioning nanostructures and functional molecules at surfaces and engineering their local coupling behavior is a key challenge in nanotechnology. The recently discovered BN nanomesh on the Rh(111) surface is a potential candidate to combine both properti ...

2008

TSPC Flip-Flop Circuit Design with Three-Independent-Gate Silicon Nanowire FETs

Giovanni De Micheli, Jian Zhang, Xifan Tang, Pierre-Emmanuel Julien Marc Gaillardon

True Single-Phase Clock (TSPC) Flip-Flops, based on dynamic logic implementation, are area-saving and high-speed compared to standard static flip-flops. Furthermore, logic gates can be embedded into TSPC flip-flops which significantly improves performance. ...

IEEE2014

pH-Sensitive Coiled-Coil Peptide-Cross-Linked Hyaluronic Acid Nanogels: Synthesis and Targeted Intracellular Protein Delivery to CD44 Positive Cancer Cells

Harm-Anton Klok, Jian Zhang

The clinical translation of protein drugs that act intracellularly is limited by the absence of safe and efficient intracellular protein delivery vehicles. Here, pH-sensitive coiled-coil peptide-cross-linked hyaluronic acid nanogels (HA-cNGs) were designed ...

American Chemical Society2018

On Temperature Dependency of Steep Subthreshold Slope in Dual-Independent-Gate FinFET

Giovanni De Micheli, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

Dual-independent-gate silicon FinFET has demonstrated a steep subthreshold slope (SS) when a positive feedback induced by weak impact ionization is triggered. In this paper, we study the temperature dependency of the steep SS by characterizing the fabricat ...

2015

On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

Eduardo Sanchez, Giovanni De Micheli, Hassan Ghasemzadeh Mohammadi, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon

This paper first explores the effects of faults on circuits implemented with controllable-polarity transistors. We propose a new fault model that suits the characteristics of these devices, and report the results of a SPICE-based analysis of the effects of ...

IEEE2015

Jian Zhang

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Top-Down Fabrication of Gate-All-Around Vertically-Stacked Silicon Nanowire FETs with Controllable Polarity

Pyridine-Based Lanthanide Complexes Combining MRI and NIR Luminescence Activities

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits

Configurable Logic Gates Using Polarity Controlled Silicon Nanowire Gate-All-Around FETs

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors

Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs

Operation regimes and electrical transport of steep slope Schottky Si-FinFETS

Dual-threshold-voltage configurable circuits with three-independent gate silicon nanowire FETs

A Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

Multiple-Independent-Gate Field-Effect Transistors for High Computational Density and Low Power Consumption

Polarity-Controllable Silicon Nanowire Transistors with Dual Threshold Voltages

Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs

Towards Functionality-Enhanced Devices: Controlling the Modes of Operation in Three-Independent-Gate Transistors

Process/Design Co-optimization of Regular Logic Tiles for Double-Gate Silicon Nanowire Transistors

Electronic decoupling and templating of Co nanocluster arrays on the boron nitride nanomesh

TSPC Flip-Flop Circuit Design with Three-Independent-Gate Silicon Nanowire FETs

pH-Sensitive Coiled-Coil Peptide-Cross-Linked Hyaluronic Acid Nanogels: Synthesis and Targeted Intracellular Protein Delivery to CD44 Positive Cancer Cells

On Temperature Dependency of Steep Subthreshold Slope in Dual-Independent-Gate FinFET

On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

Guidelines for the use and interpretation of assays for monitoring autophagy (3rd edition)