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Mirjana Stojilovic

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Related publications (39)

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A machine learning approach for power gating the FPGA routing network

Mirjana Stojilovic

Power gating is a common approach for reducing circuit static power consumption. In FPGAs, resources that dominate static power consumption lie in the routing network. Researchers have proposed several heuristics for clustering multiplexers in the routing ...

IEEE COMPUTER SOC2019

FPGA-Assisted Deterministic Routing for FPGAs

Mirjana Stojilovic

FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compile-test cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi ...

2019

A Visionary Look at the Security of Reconfigurable Cloud Computing

Francesco Regazzoni, Mirjana Stojilovic

Field-programmable gate arrays (FPGAs) have become critical components in many cloud computing platforms. These devices possess the fine-grained parallelism and specialization needed to accelerate applications ranging from machine learning to networking an ...

2023

Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs

Francesco Regazzoni, Mirjana Stojilovic, Ognjen Glamocanin, Louis Coulon

Embedded and cyber-physical systems are pervading all aspects of our lives, including sensitive and critical ones. As a result, they are an alluring target for cyber attacks. These systems, whose implementation is often based on reconfigurable hardware, ar ...

2020

A Comparator-based Technique for Identification of Intentional Electromagnetic Interference Attacks

Farhad Rachidi-Haeri, Marcos Rubinstein, Nicolas Mora Parra, Gaspard Lugrin, Mirjana Stojilovic

2014

The European Project STRUCTURES: Challenges and Results

Farhad Rachidi-Haeri, Marcos Rubinstein, Nicolas Mora Parra, Mirjana Stojilovic

2015

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Mirjana Stojilovic, Stefan Nikolic, Shashwat Shrivastava

We identified that in modern commercial FPGAs, routing signals from the general interconnect to the configurable logic blocks (CLBs) through a very sparse input interconnect block (IIB) represents a significant runtime bottleneck. This is despite academic ...

IEEE2023

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

Mirjana Stojilovic, Stefan Nikolic, Shashwat Shrivastava

This repository contains the data and software required to reproduce the results in the paper "IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck," by Shashwat Shrivastava (EPFL), Stefan Niko ...

Zenodo2023

RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks

David Spielmann, Mirjana Stojilovic, Ognjen Glamocanin

State-of-the-art sensors for measuring FPGA voltage fluctuations are time-to-digital converters (TDCs). They allow detecting voltage fluctuations in the order of a few nanoseconds. The key building component of a TDC is a delay line, typically implemented ...

2023

Development of a Lightning Location System Based on Electromagnetic Time Reversal: Technical Challenges and Expected Gain

Marcos Rubinstein, Mirjana Stojilovic

The basic principles on which commercial Lightning Location Systems are based have not changed since their inception and the research and innovation efforts in the field have been essentially aimed at refining the location accuracy and at improving the dis ...

2018

Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs

Mirjana Stojilovic, Andrea Guerrieri, Seyedeh Sharareh Mirzargar

In this work, we present an automated approach for locating power-wasting attackers in shared FPGAs. In this approach, the FPGA shell is responsible for, first, placing the user designs and, second, inserting voltage sensors in a nonintrusive and adaptive ...

IEEE COMPUTER SOC2020

X-Attack: Remote Activation of Satisfiability Don’t-Care Hardware Trojans on Shared FPGAs

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud

Albeit very appealing, FPGA multitenancy in the cloud computing environment is currently on hold due to a number of recently discovered vulnerabilities to side-channel attacks and covert communication. In this work, we successfully demonstrate a new attack ...

IEEE2020

Active Wire Fences for Multitenant FPGAs

Mirjana Stojilovic, Ognjen Glamocanin

When spatially shared among multiple tenants, field-programmable gate arrays (FPGAs) are vulnerable to remote power side-channel analysis attacks. Using carefully crafted on-chip voltage sensors, adversaries can extract secrets (e.g., encryption keys or th ...

2023

GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors

Mirjana Stojilovic

A graph H is a minor of a second graph G if G can be transformed into H by two operations: 1) deleting nodes and/or edges, or 2) contracting edges. Coarse-grained reconfigurable array (CGRA) application mapping is closely related to the graph minor problem ...

Los Alamitos2023

Deep Learning Detection of GPS Spoofing

Mirjana Stojilovic

Unmanned aerial vehicles (UAVs) are widely deployed in air navigation, where numerous applications use them for safety-of-life and positioning, navigation, and timing tasks. Consequently, GPS spoofing attacks are more and more frequent. The aim of this wor ...

Springer, Cham2022

FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis

Lucas Ramirez, Louis Coulon, Paolo Ienne, Mirjana Stojilovic

Reconfigurable computing fabrics include FPGAs and CGRAs. FPGAs offer flexible bit-level reconfigurability and can map almost any program via high-level synthesis (HLS) compilers, but they incur high area and speed overheads compared to ASICs. CGRAs, in co ...

ACM Association for Computing Machinery2025

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Philip Brisk, Mirjana Stojilovic

RePlAce is a state-of-the-art prototype of a flat, analytic, and nonlinear global cell placement algorithm, which models a placement instance as an electrostatic system with positively charged objects. It can handle large-scale standard-cell and mixed-cell ...

IEEE2020

A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time

Mirjana Stojilovic

Side-channel CPU disassembly is a side-channel attack that allows an adversary to recover instructions executed by a processor. Not only does such an attack compromise code confidentiality, it can also reveal critical information on the system’s internals. ...

IEEE2022

Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud

Given the need for efficient high-performance computing, computer architectures combining CPUs, GPUs, and FPGAs are nowadays prevalent. However, each of these components suffers from electrical-level security risks. Moving to heterogeneous systems, with th ...

2022