Publications by Grace Zgheib | EPFL Graph Search

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The design and development of innovative FPGA architectures hinge on the flexibility of its toolchain. Retargetable toolchains, like the Verilog-to-Routing (VTR) flow, have been developed to enable the testing of new FPGAs by mapping circuits onto easily-d ...

Hard-wired carry chains in FPGAs are designed to improve efficiency of important arithmetic primitives. Although they are proven to be effective for arithmetic-rich functions, there are very few studies on the optimization opportunities of carry chains for ...

The idea of introducing dedicated, fast paths between certain FPGA elements in order to reduce delay is neither new nor particularly hard to come up with. What is less obvious, however, is how to put such paths to actual use. In this work, we propose an ef ...

Carry chains facilitate the implementation of adders and improve the performance of arithmetic circuits in FPGAs. The last version of the commonly used open-source Verilog-to-Routing (VTR) CAD flow now enables modelling carry chains in FPGA architectures. ...

In this work, we develop timing-driven CAD support for FPGA architectures with direct connections between LUTs. We do so by proposing an efficient ILP-based detailed placer, which moves a carefully selected subset of LUTs from their original positions, so ...

New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels ...

Technology scaling makes metal delay ever more problematic, but routing between Look-Up Tables (LUTs) still passes through a series of transistors. It seems wise to avoid the corresponding delay whenever possible. Direct connections between LUTs, both with ...

The And-Inverter Cone has been introduced as an alternative logic element to the look-up table in FPGAs, since it improves their performance and resource utilization. However, further analysis of the AIC design showed that it suffers from the delay discrep ...

Grace Zgheib

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Leading the Blind : Automated Transistor-Level Modeling for FPGA Architects

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains

Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths

Improved carry chain mapping for the VTR flow

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Non-LUT field-programmable gate arrays

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element

Automatic wire modeling to explore novel FPGA architectures

Evaluating FPGA clusters under wide ranges of design parameters

FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures

A technology mapper for depth-constrained FPGA logic cells