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Endri Bezati

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Related publications (41)

Page 2 of 3

Automated Design Flow for Multi-Functional Dataflow-Based Platforms

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application co ...

Springer Verlag2015

Generating hardware and software for RISC-V cores generated with Rocket Chip generator

Endri Bezati

This paper presents the hardware/software generation backend of a code generation framework. The backend aims at synthesizing complete systems based on RISC-V cores with accelerators from a single-language description. The framework takes the dataflow desc ...

IEEE2021

Methods to explore design space for MPEG RMC codec specifications

Marco Mattavelli, Endri Bezati, Simone Casale Brunet, Ghislain Roquier, Richard Thavot

The recent MPEG Reconfigurable Media Coding (RMC) standard aims at defining media processing specifications (e.g. video codecs) in a form that abstracts from the implementation platform, but at the same time is an appropriate starting point for implementat ...

Elsevier Science Bv2013

Trace-based manycore partitioning of stream-processing applications

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Malgorzata Maria Michalska

Application performance on these processor array platforms is highly sensitive to how functionality is physically placed on the device, as this choice crucially determines communication latencies and congestion patterns of the on-chip inter-core communicat ...

2016

Programming Heterogeneous CPU-GPU Systems by High-Level Dataflow Synthesis

Marco Mattavelli, Endri Bezati, Aurélien François Gilbert Bloch

Heterogeneous processing platforms combining in various architectures CPUs, GPUs, and programmable logic, are continuously evolving providing at each generation higher theoretical levels of computing performance. However, the challenge of how efficiently s ...

IEEE2020

High-Precision Performance Estimation of Dynamic Dataflow Programs

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Malgorzata Maria Michalska

An important challenge for a dataflow designer is to efficiently explore the design space in order to find a set of configurations that satisfy the defined objective function. The exploration directions may involve the partitioning, scheduling and buffer d ...

2016

Synthesis and optimization of high-level stream programs

Marco Mattavelli, Endri Bezati, Simone Casale Brunet

In this paper we address the problem of translating high-level stream programs, such as those written in MPEG's RVC-CAL dataflow language, into implementations in programmable hardware. Our focus is on two aspects: sufficient language coverage to make synt ...

2013

Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

IEEE2014

MPEG high efficient video coding stream programming and many-cores scalability

Marco Mattavelli, Endri Bezati, Simone Casale Brunet, Daniele Renzi, Malgorzata Maria Michalska, Damien Jack De Saint Jorre

2014

Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism

Marco Mattavelli, Endri Bezati, Aurélien François Gilbert Bloch

This paper presents new optimization approaches aiming at reducing the impact of memory accesses on the performance of dataflow programs. The approach is based on introducing a high level management of composite data types in dynamic dataflow programming l ...

2019

Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Claudio Paolo Alberti

In this paper we propose a design methodology to partition dataflow applications on a multi clock domain architecture. This work shows how starting from a high level dataflow representation of a dynamic program it is possible to reduce the overall power co ...

Ieee2013

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

Marco Mattavelli, Endri Bezati, Ghislain Roquier, Richard Thavot

The potential computational power of today multicore processors has drastically improved compared to the single processor architecture. Since the trend of increasing the processor frequency is almost over, the competition for increased performance has move ...

Springer Heidelberg2014

Coarse Grain Clock Gating Of Streaming Applications In Programmable Logic Implementations

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

Streaming applications describe a broad class of computing algorithms in areas such as signal processing, media coding and compression, cryptography, video analytics, network touting and packet processing and many others. For many of these applications, pr ...

Ieee2014

Hardware/Software Co-Design of Dataflow Programs for Reconfigurable Hardware and Multi-Core Platforms

Marco Mattavelli, Endri Bezati, Ghislain Roquier, Richard Thavot

2011

Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs

Marco Mattavelli, Endri Bezati, Ghislain Roquier

2012

Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program

Marco Mattavelli, Endri Bezati, Simone Casale Brunet, Richard Thavot, Ab Al Hadi Bin Ab Rahman

This paper presents some strategies for design space exploration of FPGA-based signal processing systems that are specified using the CAL dataflow language. The actor- oriented, high-level of abstraction provided by CAL allows flexible exploration and cons ...

2012

TURNUS: An open-source design space exploration framework for dynamic stream programs

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

IEEE2014

Live demonstration: High level software and hardware synthesis of dataflow programs

Marco Mattavelli, Endri Bezati, Ghislain Roquier

This paper describes and demonstrates a toolchain which enables HW-SW co-synthesis from a single high-level dataflow program. This toolchain does not only enable rapid-prototyping of complex designs, but also provides a complete system integration framewor ...

2013

Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications

Marco Mattavelli, Endri Bezati, Simone Casale Brunet, Claudio Paolo Alberti

2013

A Unified Hardware/Software Co-Synthesis Solution for Signal Processing Systems

Marco Mattavelli, Endri Bezati

2011