Publications by Vasileios Pavlidis

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Clock distribution networks are affected by different sources of variations. The resulting clock uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical model of skitter, which consists of clock skew and jitter ...

In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock s ...

Three-dimensional (3-D) integration is an emerging candidate for implementing high performance multifunctional systems-on-chip. Employing an efficient medium for data communication among different planes is a key factor in achieving a high performance 3-D ...

Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (TSVs) in most of the manufacturing techniques for three-dimensional (3-D) cir ...

Global interconnect design for threedimensional integrated circuits is a crucial task. Despitethe importance of this task, limited results related to global issues have been presented. Challenges in reliably distributing power, ground, and the clock signal ...

Two diverse manufacturing techniques for building 3-D integrated systems are vertical integration with Through-Silicon-Vias (TSVs), also referred to as 3-D TSV integration, and 3-D monolithic integration. In this paper, we present a hybrid integration sche ...

A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used ...

Vasileios Pavlidis

Chat with Graph Search

Timing Uncertainty in 3-D Clock Trees due to Process Variations and Power Supply Noise

The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter

Inter-Plane Communication Methods for 3-D ICs

Power Distribution Paths for 3-D IC

Clock and Power Distribution Networks for 3-D ICs

3.5-D Integration: A Case Study

Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits

Enhanced Wafer Matching Heuristics for 3-D ICs