Publications by Vincenzo Rana | EPFL Graph Search

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The performance and the efficiency of recent computing platforms have been deeply influenced by the widespread adoption of hardware accelerators, such as Graphics Processing Units (GPUs) or Field Programmable Gate Arrays (FPGAs), which are often employed t ...

Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhanced support for dynamic and partial reconfigurability. Design automation suppor ...

The role of Field-Programmable Gate Arrays (FPGAs) in System-on-Chip (SoC) design considerably increased in the last few years. Their established importance is due to the large amount of hardware resources they offer, as well as to their increasing perform ...

The complexity of Wireless Sensor Networks (WSNs) has been constantly increasing over the last decade, and the necessity of efficient CAD tools has been growing accordingly. In fact, the size of the design space of a WSN has become large, and an exploratio ...

Nowadays, multi-core Systems-on-Chip (SoCs) are typically required to execute multiple complex applications, which demand a large set of heterogeneous hardware cores with different sizes. In this context, the popularity of dynamically reconfigurable platfo ...

The determination of the optical flow is a central problem in image processing, as it allows to describe how an image changes over time by means of a numerical vector field. The estimation of the optical flow is however a very complex problem, which has be ...

Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systems on Chips (SoCs). However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of runn ...

Wireless sensor networks (WNSs) are gradually evolving from a promising technology to a well-established reality in a large set of different domains. In order to fulfill the requirements of the specific scenario, a WSN must provide the right tradeoffs betw ...

Traditionally, parallel implementations of multimedia algorithms are carried out manually, since the automation of this task is very difficult due to the complex dependencies that generally exist between different elements of the data set. Moreover, there ...

Reconfigurable platforms are a promising technology that offers an interesting trade-off between flexibility and performance, which many recent embedded system applications demand, especially in fields such as multimedia processing. These applications typi ...

Wireless body sensor networks (WBSNs) are a rising technology that allows constant and unobtrusive monitoring of the vital signals of a patient. The configuration of a WBSN node proves to be critical in order to maximize its lifetime, while meeting the pre ...

The automatic generation of hardware implementations for a given algorithm is generally a difficult task, especially when data dependencies span across multiple iterations such as in iterative stencil loops (ISLs). In this paper, we introduce an automatic ...

A large number of algorithms for multidimensional signals processing and scientific computation come in the form of iterative stencil loops (ISLs), whose data dependencies span across multiple iterations. Because of their complex inner structure, automatic ...

Nowadays, hardware devices are meant to host the execution of many complex, multi-core applications, whose functional and non-functional requirements vary according to the specific working domain. In this work, we propose a design methodology that combines ...

Reconfigurable computing is a promising technology that offers an interesting trade-off between flexibility and performance, which many recent multi-core embedded system applications demand. In order to achieve these objectives, it is necessary to optimize ...

The increasing popularity of multi-core System-on-Chip platforms introduces new challenges, both in terms of hardware platforms and design methodologies. Dynamic reconfiguration can be exploited to increase the flexibility of the system and to implement mu ...

Vincenzo Rana

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Parallelizing the Chambolle Algorithm for Performance Optimized Mapping on FPGA devices

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems

Run-time Mapping of Applications on FPGA-based Reconfigurable Systems

Knowledge-based design space exploration of wireless sensor networks

A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design

A High–Performance Parallel Implementation of the Chambolle Algorithm

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

Design Exploration of Energy-Performance Trade-offs for Wireless Sensor Networks

Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms

A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms

Model-Based Design for Wireless Body Sensor Network Nodes

A High-Level Synthesis Flow for the Implementation of Iterative Stencil Loop Algorithms on FPGA Devices

Efficient Hardware Design Of Iterative Stencil Loops

Island-Based Adaptable Embedded System Design

A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware

Run-Time Mapping for Dynamically-Added Applications in Reconfigurable Embedded Systems