Publications by Babak Falsafi | EPFL Graph Search

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Memory hierarchy in Graphics Processing Units (GPUs) is conventionally designed to provide high bandwidth rather than low latency. In particular, because of the high tolerance to load-to-use latency (i.e., the time that warps wait for data fetched by memor ...

Function-as-a-Service (FaaS) has emerged as a popular cloud paradigm that simplifies software development and deployment by providing scalable and event-driven function execution without the burden of managing servers. FaaS was originally created with a fu ...

Many hardware optimizations rely on collecting information about program behavior at runtime. This information is stored in lookup tables. To be accurate and effective, these optimizations usually require large dedicated on-chip tables. Although technology ...

In-memory databases rely on pointer-intensive data structures to quickly locate data in memory. A single lookup operation in such data structures often exhibits long-latency memory stalls due to dependent pointer dereferences. Hiding the memory latency by ...

The emerging paradigm of microservices decomposes online services into fine-grained software modules frequently communicating over the datacenter network, often using Remote Procedure Calls (RPCs). Ongoing advancements in the network stack have exposed the ...

Intuitively, aggressive work sharing among concurrent queries in a database system should always improve performance by eliminating redundant computation or data accesses. We show that, contrary to common intuition, this is not always the case in practice, ...

Instruction-grain monitoring is a powerful approach that enables a wide spectrum of bug-finding tools. As existing software approaches incur prohibitive runtime overhead, researchers have focused on hardware support for instruction-grain monitoring. A recu ...

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, ...

To provide low latency and high throughput guarantees, most large key-value stores keep the data in the memory of many servers. Despite the natural parallelism across lookups, the load imbalance, introduced by heavy skew in the popularity distribution of k ...

In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses, soft and hard errors in the memory system will increase and single error ev ...

Traditional reliable servers require costly design changes to the processor, use custom system or application software, or cannot scale beyond a few processing elements. We present TRUSS, a family of server architectures providing reliable, scalable comput ...

Server chips will not scale beyond a few tens to low hundreds of cores, and an increasing fraction of the chip in future technologies will be dark silicon that we cannot afford to power. Specialized multicore processors, however, can leverage the underutil ...

Instruction-grain lifeguards monitor executing programs at the granularity of individual instructions to quickly detect bugs and security attacks, but their fine-grain nature incurs high monitoring overheads. This article identifies three common sources of ...

Performance and total cost of ownership (TCO) are key optimization metrics in large-scale data centers. According to these metrics, data centers designed with conventional server processors are inefficient. Recently introduced processors based on low-power ...

The growing explosion of digital data motivates renewed emphasis on new architectures for future data-centric workloads. At the same time, the inability of power to scale with increasing transistor counts has led to a recent focus on “dark silicon” designs ...

Despite a decade of research demonstrating its efficacy, address-correlated prefetching has never been implemented in a shipping processor because it requires megabytes of metadata—too large to store practically on chip. New storage-, latency-, and bandwid ...

Datacenter operators have started deploying Persistent Memory (PM), leveraging its combination of fast access and persistence for significant performance gains. A key challenge for PM-aware software is to maintain high performance while achieving atomic du ...

Precise exceptions are a cornerstone of modern computing as they provide the abstraction of sequential instruction execution to programmers while accommodating microarchitectural optimizations. However, increasing compute capabilities in deep memory hierar ...

Babak Falsafi

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A Low-latency On-chip Cache Hierarchy for Load-to-use Stall Reduction in GPUs

Single-Address-Space FaaS with Jord

Predictor virtualization

Asynchronous memory access chaining

Cerebros: Evading the RPC Tax in Datacenters

To Share or Not To Share?

FADE: A Programmable Filtering Accelerator for Instruction-Grain Monitoring

DeSyRe: On-demand system reliability

The Case for RackOut: Scalable Data Serving Using Rack-Scale Systems

Multi-bit error tolerant caches using two-dimensional error coding

TRUSS: A Reliable, Scalable Server Architecture

Toward Dark Silicon in Servers

SHIFT: Shared History Instruction Fetch for Lean-Core Server Processors

Flexible Hardware Acceleration for Instruction-Grain Lifeguards

Optimizing Data-Center TCO with Scale-Out Processors

Dark Silicon Accelerators for Database Indexing

Making Address-Correlated Prefetching Practical

Distributed Logless Atomic Durability with Persistent Memory

What's Missing in Agile Hardware Design? Verification!

Imprecise Store Exceptions