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Romuald Mosqueron

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Related publications (7)

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Smart camera with embedded co-processor: a postal sorting application

Marco Mattavelli, Romuald Mosqueron

This work describes an image acquisition and processing system based on a new co-processor architecture designed for CMOS sensor imaging. The platform permits to configure a wide variety of acquisition modes (random region acquisition, variable image size, ...

2008

An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms

Marco Mattavelli, Endri Bezati, Simone Casale Brunet, Romuald Mosqueron

In recent years, the number and variety of heterogeneous multiprocessor system-on-chip MPSoCs, such as for instance Zynq platforms, has sensibly increased. However, today all design flow solutions capable of programming the different components of such pla ...

IEEE2019

Smart camera based on embedded HW/SW coprocessor

Marco Mattavelli, Romuald Mosqueron

This paper describes an image acquisition and a processing system based on a new coprocessor architecture designed for CMOS sensor imaging. The system exploits the full potential CMOS selective access imaging technology because the coprocessor unit is inte ...

2008

Hardware synthesis of complex standard interfaces using CAL dataflow descriptions

Marco Mattavelli, Richard Thavot, Romuald Mosqueron

This paper presents a contribution to the development of rapid prototyping tools based on data-flow description. In this context, the efficiency of automatic translator tools from the data-flow description to C and/or HDL are presented using two design cas ...

2009

Romuald Mosqueron

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Smart camera with embedded co-processor: a postal sorting application

An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms

Smart camera based on embedded HW/SW coprocessor

Hardware synthesis of complex standard interfaces using CAL dataflow descriptions

High Performance Embedded Co-Processor Architecture For CMOS Imaging Systems

Motion estimation accelerator with user search strategy for the RVC framework

Dataflow design of a co-processor architecture for image processing