Publications by Ciprian Seiculescu

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

As the complexity of applications grows with each new generation, so does the demand for computation power. To satisfy the computation demands at manageable power levels, we see a shift in the design paradigm from single processor systems to Multiprocessor ...

Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient network on chip (NoC) interconnect for a 3-D SoC that meets not only the applicat ...

Manycore chips are emerging as the architecture of choice to provide power efficiency and improve performance, while riding Moore’s Law. In these architectures, on-chip interconnects play a pivotal role in ensuring power and performance scalability. As sup ...

Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (NoCs) are necessary to efficiently handle the 3D interconnect complexity. Desi ...

Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as ...

Achieving the main memory (DRAM) required bandwidth at ac- ceptable power levels for current and future applications is a ma- jor challenge for System-on-Chip designers for mobile platforms. Three dimensional (3D) integration and 3D stacked DRAM mem- ories ...

Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in t ...

Two diverse manufacturing techniques for building 3-D integrated systems are vertical integration with Through-Silicon-Vias (TSVs), also referred to as 3-D TSV integration, and 3-D monolithic integration. In this paper, we present a hybrid integration sche ...

In many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power consumption. However, today, the interconnect architecture is a bottleneck in ...

Ciprian Seiculescu

Chat with Graph Search

Design Methods and Tools for Application-Specific Predictable Networks-on-Chip

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips

CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers

Synthesis of Networks on Chips for 3D Systems on Chips

Networks on Chips: From Research to Products

A Distributed Interleaving Scheme for Efficient Access to WideIO DRAM Memory

Designing Best Effort Networks-on-Chip to Meet Hard Latency Constraints

3.5-D Integration: A Case Study

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chip

NoC Topology Synthesis for Supporting Shutdown of Voltage Islands in SoCs