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Luca Benini

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Related publications (77)

Page 4 of 4

A Distributed Interleaving Scheme for Efficient Access to WideIO DRAM Memory

Giovanni De Micheli, Luca Benini, Ciprian Seiculescu

Achieving the main memory (DRAM) required bandwidth at ac- ceptable power levels for current and future applications is a ma- jor challenge for System-on-Chip designers for mobile platforms. Three dimensional (3D) integration and 3D stacked DRAM mem- ories ...

2012

Designing Best Effort Networks-on-Chip to Meet Hard Latency Constraints

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu, Hamid Sarbazi-Azad, Dara Rahmati

Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in t ...

Assoc Computing Machinery2013

A Method to Remove Deadlocks in Networks-on-Chips with Wormhole Flow Control

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Networks-on-Chip (NoCs) are a promising interconnect paradigm to address the communication bottleneck of Systems-on-Chip (SoCs). Wormhole flow control is widely used as the transmission protocol in NoCs, as it offers high throughput and low latency. To mat ...

2010

Networks on Chips: 15 Years Later

Giovanni De Micheli, Luca Benini

The authors of a Computer article from 2002 reflect on their proposal to use networks on chips to address scalable communications on silicon VLSI chips. ...

2017

Cancer marker detection in human serum with a point-of-care low-cost system

Sandro Carrara, Luca Benini

Chemiluminescence, i.e. the emission of light from a chemical reaction, offers interesting opportunities for developing point-of-care biosensors. However, commercially available systems are expensive, bulky, and primarily addressed to laboratory usage. The ...

2010

A Multi-Path Routing Strategy with Guaranteed In-order Packet Delivery and Fault Tolerance for Networks on Chips

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali

In this work we present a multi-path routing strategy that guarantees in-order packet delivery for Networks on Chips (NoCs). We present a design methodology that uses the routing strategy to optimally spread the traffic in the NoC to minimize the network b ...

2006

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Federico Angiolini, Hamid Sarbazi-Azad, Dara Rahmati

Real-time (RT) communication support is a critical requirement for many complex embedded applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper, we present novel methods to efficiently calculate worst- case bandwidth an ...

Institute of Electrical and Electronics Engineers2013

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

Andreas Peter Burg, Luca Benini, Adam Shmuel Teman, Jeremy Hugues-Felix Constantin

This article presents an ultra-low-power parallel computing platform and its system-on-chip (SoC) embodiment, targeting a wide range of emerging near-sensor processing tasks for Internet of Things (IoT) applications. The proposed SoC achieves 193 million o ...

Institute of Electrical and Electronics Engineers2017

Improving the Fault Tolerance of Nanometric PLA Designs

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Federico Angiolini, Mohamed Haykel Ben Jamaa

Several alternative building blocks have been proposed to replace planar transistors, among which a prominent spot belongs to nanometric laments such as Silicon NanoWires (SiNWs) and Carbon NanoTubes (CNTs). However, chips leveraging these nanoscale struct ...

2007

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

Giovanni De Micheli, Luca Benini

The use of multi-core clusters is a promising option for data-intensive embedded applications such as multi-modal sensor fusion, image understanding, mobile augmented reality. In this paper, we propose a power-efficient 3-D on-chip interconnect for multi-c ...

IEEE2016

Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures

Giovanni De Micheli, David Atienza Alonso, Luca Benini

As feature sizes decrease, power dissipation and heat generation density exponentially increase. Thus, temperature gradients in Multiprocessor Systems on Chip (MPSoCs) can seriously impact system performance and reliability. Thermal balancing policies base ...

2008

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chip

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

2009

A Method for Calculating Hard QoS Guarantees for Networks-on-Chip

Dara Rahmati, Giovanni De Micheli, Luca Benini, Srinivasan Murali, Federico Angiolini, Hamid Sarbazi-Azad

Many Networks-on-Chip (NoC) applications exhibit one or more critical traffic flows that require hard Quality of Service (QoS). Guaranteeing bandwidth and latency for such real time flows is crucial. In this paper, we present novel methods to efficiently c ...

2009

A Novel Approach for Network on Chip Emulation

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Nicolas Genko

Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoCs can have regular or a ...

2005

NoC Topology Synthesis for Supporting Shutdown of Voltage Islands in SoCs

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

In many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power consumption. However, today, the interconnect architecture is a bottleneck in ...

2009

Bringing NoCs to 65nm

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of Noc-Based interconnect design in nanometer CMOS. The aut ...

2007

Enabling Efficient Hybrid Systolic Computation in Shared-L1-Memory Manycore Clusters

Luca Benini

Institute of Electrical and Electronics Engineers (IEEE)2024