Publications by Luca Benini | EPFL Graph Search

Related publications (77)

New insights for using self-assembly materials to improve the detection stability in label-free DNA-chip and immuno-sensors

Sandro Carrara, Luca Benini, Andrea Cavallini, Anna Ferretti, Bruno Samori

This paper examines reliable advancements in low-cost DNA- and immuno-chips. Capacitance detection was successfully chosen to develop label-free bio-chips. Probe immobilization was rigorously investigated in order to obtain reliable capacitance measurement ...

Elsevier2009

Bioimaging and Functional Genomics

Giovanni De Micheli, Luca Benini

For better understanding of genetic mechanisms underlying clinical observations, it is interesting to determine which genes and clinical traits are interrelated. In the last few years a consistent amount of research in genomics has been done concerning cor ...

2006

Online Thermal Control Methods for Multi-Processor Systems

Giovanni De Micheli, David Atienza Alonso, Colin Neil Jones, Luca Benini, Francesco Zanini

With technological advances, the number of cores integrated on a chip is increasing. This, in turn is leading to thermal constraints and thermal design challenges. Temperature gradients and hot-spots not only affect the performance of the system, but also ...

Association for Computing Machinery2012

GPGPU-Accelerated Parallel and Fast Simulation of Thousand-core Platforms

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

The multicore revolution and the ever-increasing complexity of computing systems is dramatically changing system design, analysis and programming of computing platforms. Future architectures will feature hundreds to thousands of simple processors and on-ch ...

IEEE/ACM Press2011

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Giovanni De Micheli, Luca Benini

3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and l ...

Institute of Electrical and Electronics Engineers2015

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Andreas Peter Burg, Luca Benini, Adam Shmuel Teman, Pascal Andreas Meinerzhagen

Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of vendors throug ...

Association for Computing Machinery2016

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chips

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs). Designing an efficient network on chip (NoC) interconnect for a 3-D SoC that meets not only the applicat ...

2010

Low-power processor architecture exploration for online biomedical signal analysis

David Atienza Alonso, Andreas Peter Burg, Luca Benini, Jeremy Hugues-Felix Constantin, Ahmed Yasir Dogan

In this study, the authors explore sequential and parallel processing architectures, utilising a custom ultra-low-power (ULP) processing core, to extend the lifetime of health monitoring systems, where slow biosignal events and highly parallel computations ...

Inst Engineering Technology-Iet2012

Reliability-Aware Design for Nanometer-Scale Devices

Giovanni De Micheli, David Atienza Alonso, Luca Benini, José Luis Ayala Rodrigo, Pablo Garcia del Valle

Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges to maintain manufacturing yield rates and reliable devices in their expecte ...

2008

HW-SW Emulation Framework for Temperature-Aware Design in MPSoCs

Giovanni De Micheli, David Atienza Alonso, Luca Benini

New tendencies envisage Multi-Processor Systems-On-Chip (MPSoCs) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute multiple applications (games, video), while meeting additional design constrain ...

2008

Method to design network-on-chip (noc)-based communication systems

Giovanni De Micheli, Luca Benini, Srinivasan Murali

To tackle the increasing communication complexity of multi-core systems, scalable Networks on Chips (NoCs) are needed to interconnect the processor, memory and hardware cores of the systems. For the use of NoCs to be feasible in today's industrial designs, ...

2008

Real-time high-sensitivity impedance measurement interface for tethered BLM biosensor arrays

Giovanni De Micheli, Yusuf Leblebici, Horst Arthur Vogel, Luca Benini, Carlotta Guiducci, Yüksel Temiz, Samuel Terrettaz

This paper presents a switched-capacitor (SC) current integrator circuit for impedance measurement of tethered bilayer lipid membrane (tBLM) biosensors. The circuit comprises a small number of high performance components enabling enhanced experimental flex ...

2008

Towards Near-Threshold Server Processors

David Atienza Alonso, Luca Benini, Babak Falsafi, Marina Zapater Sancho, Pablo Garcia del Valle, Javier Picorel Obando, Ali Pahlevan, Arash Pourhabibi Zarandi

The popularity of cloud computing has led to a dramatic increase in the number of data centers in the world. The ever-increasing computational demands along with the slowdown in technology scaling has ushered an era of power-limited servers. Techniques suc ...

IEEE/ACM2016

GPU Acceleration for Simulating Massively Parallel Many-Core Platforms

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

Emerging massively parallel architectures such as a general-purpose processor plus many-core programmable accelerators are creating an increasing demand for novel methods to perform their architectural simulation. Most state-of-the-art simulation technolog ...

Institute of Electrical and Electronics Engineers2015

New probe immobilizations by lipoate-diethalonamine or ethylene-glycol molecules for capacitance DNA chip

Bruno Samori, Giovanni De Micheli, Yusuf Leblebici, Sandro Carrara, Luca Benini, Andrea Cavallini

Label–free DNA detection is of crucial role to when developing point-of-care biochips to be used in personalized therapy. Capacitance detection is a promising technology for label-free DNA detection. However, data published in literature often show evident ...

2009

A Portable Setup for Molecular Detection by Transmission LSPR

Luca Benini, Carlotta Guiducci, Enrico Accastelli, Giulia Cappi, Fabio Mario Spiga

In the framework of bioanalytics and multiple array detection, we developed a fully portable and low-cost detection system based on Localized Surface Plasmon Resonance (LSPR) in a transmission configuration (T-LSPR). The transmission approach is suitable t ...

2012

Efficient Sample Delay Calculation for 2-D and 3-D Ultrasound Imaging

Jean-Philippe Thiran, Giovanni De Micheli, Luca Benini, Marcel Arditi, Federico Angiolini, Aya Mohamed Naguib Ahmed Ibrahim

Ultrasound imaging is a reference medical diagnostic technique, thanks to its blend of versatility, effectiveness, and moderate cost. The core computation of all ultrasound imaging methods is based on simple formulae, except for those required to calculate ...

Ieee-Inst Electrical Electronics Engineers Inc2017

Synthesis of Predictable Networks-on-Chip Based Interconnect Architectures for Chip Multi-Processors

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali

Today, chip multiprocessors (CMPs) that accommodate multiple processor cores on the same chip have become a reality. As the communication complexity of such multicore systems is rapidly increasing, designing an interconnect architecture with predictable be ...

2007

Designing Application-Specific Networks on Chips with Floorplan Information

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

With increasing communication demands of processor and memory cores in Systems on Chips (SoCs), scalable Networks on Chips (NoCs) are needed to interconnect the cores. For the use of NoCs to be feasible in today’s industrial designs, a custom-tailored, app ...

2006

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Srinivasan Murali, Federico Angiolini

Networks on Chip (NoC) has emerged as the paradigm for designing scalable communication architecture for Systems on Chips (SoCs). Avoiding the conditions that can lead to deadlocks in the network is critical for using NoCs in real designs. Methods that can ...

2006