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David Atienza Alonso

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Related publications (385)

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HW-SW Emulation Framework for Temperature-Aware Design in MPSoCs

Giovanni De Micheli, David Atienza Alonso, Luca Benini

New tendencies envisage Multi-Processor Systems-On-Chip (MPSoCs) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute multiple applications (games, video), while meeting additional design constrain ...

2008

A Self-Learning Methodology for Epileptic Seizure Detection with Minimally Supervised Edge Labeling

David Atienza Alonso, Amir Aminifar, Damián Pascual Ortiz

Epilepsy is one of the most common neurological disorders and affects over 65 million people worldwide. Despite the continuing advances in anti-epileptic treatments, one third of the epilepsy patients live with drug resistant seizures. Besides, the mortali ...

2019

Thermal-Aware Compilation for Register Window-Based Embedded Processors

David Atienza Alonso, Mohamed Mostafa Sabry Aly

The development of compiler-based mechanisms to optimize the thermal profile of large register files to improve the processor reliability has become an important issue. Thermal hotspots have been known to cause severe reliability issues, while the thermal ...

Institute of Electrical and Electronics Engineers2010

Free Cooling-Aware Dynamic Power Management for Green Datacenters

David Atienza Alonso, Martino Ruggiero, Jungsoo Kim

Free cooling, i.e., directly using outside cold air and/or water to cool down datacenters, can provide significant power savings of datacenters. However, due to the limited cooling capability, which is tightly coupled with climate conditions, free cooling ...

IEEE Press2012

Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories

Giovanni De Micheli, Mihai Adrian Ionescu, Yusuf Leblebici, David Atienza Alonso, Didier Bouvet, Kirsten Emilie Moselund, Mohamed Haykel Ben Jamaa

The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) decoder is a critical part since it bridges the sublithographic wires to the outer circuit ...

2008

BLADE: A BitLine Accelerator for Devices on the Edge

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, William Andrew Simon, Yasir Mahmood Qureshi

The increasing ubiquity of edge devices in the consumer market, along with their ever more computationally expensive workloads, necessitate corresponding increases in computing power to support such workloads. In-memory computing is attractive in edge devi ...

2019

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Miguel Peon Quiros, Marco Antonio Rios

Resistive switching memory technologies (RRAM) are seen by most of the scientific community as an enabler for Edge-level applications such as embedded deep Learning, AI or signal processing of audio and video signals. However, going beyond a "simple'' repl ...

IEEE2020

Mixed Heuristic and Mathematical Programming Using Reference Points for Dynamic Data Types Optimization in Multimedia Embedded Systems

David Atienza Alonso

New multimedia embedded applications are becoming increasingly dynamic. Thus, they cannot only rely on static data allocation, and must employ Dynamically-allocated Data Types (DDTs) to store their data and efficiently use the limited physical resources of ...

ACM Press2009

Prospects for logic-on-a-wire

Giovanni De Micheli, Mihai Adrian Ionescu, Yusuf Leblebici, David Atienza Alonso, Didier Bouvet, Kirsten Emilie Moselund, Mohamed Haykel Ben Jamaa

In this paper we present the top-down fabrication of gate-all-around (GAA) and body-tied @W-gate devices by a combination of etching and oxidation steps resulting in a local silicon-on-insulator structure. The GAA has advantages in terms of enhanced curren ...

2008

TEE4EHR: Transformer event encoder for better representation learning in electronic health records

David Atienza Alonso, Anisoara Ionescu, Hojjat Karami

Irregular sampling of time series in electronic health records (EHRs) is one of the main challenges for developing machine learning models. Additionally, the pattern of missing values in certain clinical variables is not at random but depends on the decisi ...

2024

Approximate Zero-Crossing: A new interpretable, highly discriminative and low-complexity feature for EEG and iEEG seizure detection

David Atienza Alonso, Tomas Teijeiro Campo, Una Pale, Renato Zanetti

Objective: Long-term monitoring of people with epilepsy based on electroencephalography (EEG) and intracranial EEG (iEEG) has the potential to deliver key clinical information for personalised epilepsy treatment. More specifically, in outpatient settings, ...

2022

Integrating Heuristic and Machine-Learning Methods for Efficient Virtual Machine Allocation in Data Centers

David Atienza Alonso, Marina Zapater Sancho, Ali Pahlevan

Modern cloud data centers (DCs) need to tackle efficiently the increasing demand for computing resources and address the energy efficiency challenge. Therefore, it is essential to develop resource provisioning policies that are aware of virtual machine (VM ...

2018

SzCORE: Seizure Community Open-Source Research Evaluation framework for the validation of electroencephalography-based automated seizure detection algorithms

David Atienza Alonso, Una Pale, Alireza Amirshahi, Jonathan Dan, William Cappelletti

The need for high-quality automated seizure detection algorithms based on electroencephalography (EEG) becomes ever more pressing with the increasing use of ambulatory and long-term EEG monitoring. Heterogeneity in validation methods of these algorithms in ...

2024

3D-ICE: Fast compact transient thermal modeling for 3D-ICs with inter-tier liquid cooling

David Atienza Alonso, Martino Ruggiero, Arvind Raj Mahankali Sridhar, Alessandro Vincenzi

Three dimensional stacked integrated circuits (3D ICs) are extremely attractive for overcoming the barriers in interconnect scaling, offering an opportunity to continue the CMOS performance trends for the next decade. However, from a thermal perspective, v ...

ACM and IEEE Press2010

Fuzzy Control for Enforcing Energy Efficiency in High-Performance 3D Systems

David Atienza Alonso, Mohamed Mostafa Sabry Aly

3D stacked circuits reduce communication delay in multicore system-on-chips (SoCs) and enable heterogeneous integration of cores, memories, sensors, and RF devices. However, vertical integration of layers exacerbates the reliability and thermal problems, a ...

IEEE Press2010

LSST: From Science Drivers to Reference Design and Anticipated Data Products

David Atienza Alonso, Jonathan Andrew Blazek, Darong Huang, Shahram Khazaei

We describe here the most ambitious survey currently planned in the optical, the Large Synoptic Survey Telescope (LSST). The LSST design is driven by four main science themes: probing dark energy and dark matter, taking an inventory of the solar system, ex ...

IOP PUBLISHING LTD2019

A Multi-Lead ECG Classification Based on Random Projection Features

David Atienza Alonso, Iva Bogdanova Vandergheynst, Francisco Javier Rincon Vallejos

This paper presents a novel method for classification of multilead electrocardiogram (ECG) signals. The feature extraction is based on the random projection (RP) concept for dimensionality reduction. Furthermore, the classification is performed by a neuro- ...

IEEE Press2012

Dynamic Thermal Management in 3D Multicore Architectures

Yusuf Leblebici, David Atienza Alonso, José Luis Ayala Rodrigo

Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently proposed approach to overcome the power consumption and dela ...

IEEE and ACM2009

SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs

David Atienza Alonso, Giovanni Ansaloni, José Angel Miranda Calero, Benoît Walter Denkinger, Juan Pablo Sapriza Araujo, Ruben Rodriguez, Rubén Rodríguez Álvarez

Coarse-Grain Reconfigurable Arrays (CGRAs) represent emerging low-power architectures designed to accelerate Compute-Intensive Loops (CILs). The effectiveness of CGRAs in providing acceleration relies on the quality of mapping: how efficiently the CIL is c ...

2024

A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing

David Atienza Alonso, Luca Benini, Giovanni Ansaloni, Ruben Braojos Lopez

In the last decade, improvements on technology scaling have enabled the design of a novel generation of wearable bio-sensing monitors. These smart Wireless Body Sensor Nodes (WBSNs) are able to acquire and process biological signals, such as electrocardiog ...

Institute of Electrical and Electronics Engineers2017