Publications by Giovanni De Micheli

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In this paper, we present biconditional binary deci- sion diagrams (BBDDs), a novel canonical representation form for Boolean functions. BBDDs are binary decision diagrams where the branching condition, and its associated logic expansion, is biconditional ...

This work demonstrates the first fabricated 4-transistor logic gates using polarity-configurable, gate-all- around silicon nanowire transistors. This technology enhances conventional CMOS functionality by adding the degree of free- dom of dynamic polarity ...

Vertically-stacked Silicon NanoWire FETs (SiN- WFETs) with gate-all-around control are the natural and most advanced extension of FinFETs. At advanced technology nodes, due to Schottky contacts at channel interfaces, devices show an ambipolar behavior, i.e ...

Today's embedded systems integrate multiple IP cores for processing, communication, and sensing on a single die as systems-on-chip (SoCs). Aggressive transistor scaling, decreased voltage margins and increased processor power and temperature have made reli ...

Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic, and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal dev ...

Carbon Nanotubes (CNTs) are grown using chemical synthesis, and the exact positioning and chirality of CNTs are very difficult to control. As a result, “small-width” Carbon Nanotube Field-Effect Transistors (CNFETs) can have a high probability of containin ...

We present a novel integrated circuit for a biosensing data acquisition chain. The circuit controls and reads out five bimolecular sensors as well as pH and temperature sensors for biosensor calibration. The IC supports both chronoamperometry (CA) a ...

Silicon nanowires are a promising solution to address the increasing challenges of fabrication and design at the future nodes of the Complementary Metal-Oxide-Semiconductor (CMOS) Technology roadmap. Despite the attractive opportunity that offers their org ...

Emerging technologies such as plasmonics and photonics are promising alternatives to CMOS for high throughput applications, thanks to their waveguide's low power consumption and high speed of computation. Besides these qualities, these novel technologies a ...

Exact synthesis is a versatile logic synthesis technique with applications to logic optimization, technology mapping, synthesis for emerging technologies, and cryptography. In recent years, advances in SAT solving have lead to a heightened research effort ...

A method for transforming a tautology check of an original logic circuit into a contradiction check of the original logic circuit and vice versa comprises interpreting the original logic circuit in terms of AND, OR, MAJ, MIN, XOR, XNOR, INV original logic ...

This paper discusses the newly introduced vertically-stacked silicon nanowire gate-all-around fieldeffect-transistor technology and its advantages for higher density layout design. The vertical nanowire stacking technology allows very-high density arrangem ...

With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are very complex to design as they must execute multiple co ...

Today's rapid advances in the physical implementation of quantum computers demand for scalable synthesis methods in order to map practical logic designs to quantum architectures. We present a synthesis algorithm for quantum computing based on k-LUT network ...

Despite the huge research effort to improve the performance of the complementary metal oxide semiconductor (CMOS) image sensors, charge-coupled devices (CCDs) still dominate the cell biology-related conventional fluorescence microscopic imaging market wher ...

Rapid single-flux quantum (RSFQ) is one of the most advanced superconducting technologies with the potential to supplement or replace conventional VLSI systems. However, scaling RSFQ systems up to VLSI complexity is challenging due to fundamental differenc ...

In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock s ...

The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects necessary for today’s grail in CNFET technology, achieving functional immunity ...

As scaling of conventional silicon-based electronics is reaching its ultimate limit, considerable effort has been devoted to find new materials and new device concepts that could ultimately outperform standard silicon transistors. In this perspective two-d ...

Currently, there is a large research interest and a significant economical effort to build the first practical quantum computer. Such quantum computers promise to exceed the capabilities of conventional computers in fields such as computational chemistry, ...

Giovanni De Micheli

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Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form

Configurable Logic Gates Using Polarity Controlled Silicon Nanowire Gate-All-Around FETs

Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: a Robustness Study

Power and Reliability Management of SoCs

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

Carbon Nanotube Correlation: Promising Opportunity for CNFET Circuit Yield Enhancement

A Configurable IC to Control, Readout and Calibrate an Array of Biosensors

Decoding Nanowire Arrays Fabricated with the Multi-Spacer Patterning Technique

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic

SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism

Method for speeding up boolean satisfiability

Design Aspects of Carry Lookahead Adders with Vertically-Stacked Nanowire Transistors

Architectural Exploration of MPSoC Designs Based on an FPGA Emulation Framework

Hierarchical Reversible Logic Synthesis Using LUTs

Empowering Low-Cost CMOS Cameras by Image Processing to Reach Comparable Results with Costly CCDs

Synthesis of SFQ Circuits with Compound Gates

The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter

Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis

Polarity control in WSe2 double-gate transistors

A Best-Fit Mapping Algorithm to Facilitate ESOP-Decomposition in Clifford+T Quantum Network Synthesis