Publications by Giovanni De Micheli

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Today, chip multiprocessors (CMPs) that accommodate multiple processor cores on the same chip have become a reality. As the communication complexity of such multicore systems is rapidly increasing, designing an interconnect architecture with predictable be ...

In this paper we propose CMOS-compatible Memristive-Biosensors as label-free, highly sensitive sensors for in-air detection of Vascular Endothelial Growth Factor (VEGF) molecules. The memristive behavior of the fabricated devices is strongly affec ...

Regenerative medicine is a novel clinical branch aiming at the cure of diseases by replacement of damaged tissues. The crucial use of stem cells makes this area rich of challenges, given the poorly understood mechanisms of differentiation. One highly neede ...

The aim of the present invention is to propose a method to provide reliability, power management and load balancing support for multicore systems based on Networks- on-Chip (NoCs) as well as a way to efficiently implement architectural support for this met ...

Recent advances in microelectronics and biosensors are enabling developments of innovative biochips for advanced healthcare by providing fully integrated platforms for continuous monitoring of a large set of human disease biomarkers. Continuous monitoring ...

Nanowire Field Effect Transistors (FETs) with multiple independent gates around a silicon channel feature ultimate gate control and are regarded as promising candidates for next generation transistors. Being inherently more complex than conventional gate-a ...

The economic and social demand for ubiquitous and multifaceted electronic systems-in combination with the unprecedented opportunities provided by the integration of various manufacturing technologies-is paving the way to a new class of heterogeneous integr ...

Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low power alternatives to con- ventional ...

This paper presents a lightweight cryptographic system integrated onto a multi-function implantable biosensor prototype. The resulting heterogeneous system provides a unique and fundamental capability by immediately encrypting and signing the sensor data u ...

Hard-wired carry chains in FPGAs are designed to improve efficiency of important arithmetic primitives. Although they are proven to be effective for arithmetic-rich functions, there are very few studies on the optimization opportunities of carry chains for ...

Volumetric ultrasound (US) is a very promising development of medical US imaging. An under-exploited advantage of volumetric US is the mitigation of the strict probe positioning constrains necessary to acquire 2D scans, potentially allowing the decoupling ...

SAT-sweeping is a powerful method for simplifying logic networks. It consists of merging gates that are proven equivalent (up to complementation) by running simulation and SAT solving in synergy. SAT-sweeping is used in both verification and synthesis appl ...

With increasing communication demands of processor and memory cores in Systems on Chips (SoCs), scalable Networks on Chips (NoCs) are needed to interconnect the cores. For the use of NoCs to be feasible in today’s industrial designs, a custom-tailored, app ...

We address the problem of minimizing the area of circuits mapped to a technology library, with or without delay constraints. While traditional methods optimize first a technology-independent representation and then perform technology mapping to a library, ...

Networks on Chip (NoC) has emerged as the paradigm for designing scalable communication architecture for Systems on Chips (SoCs). Avoiding the conditions that can lead to deadlocks in the network is critical for using NoCs in real designs. Methods that can ...

The quest for technologies with superior device characteristics has showcased Carbon-Nanotube Field-Effect Transistors (CNFET) into limelight. In this work we present physical design techniques to improve the yield of CNFET circuits in the presence of Carb ...

The Nano-Tera.CH initiative is a broad engineering program in Switzerland for health and security of humans and the environment, currently funded by the Swiss government. The program rationale is rooted in advances in engineering nano-scale materials and t ...

We report on a fully CMOS compatible fabrication method for ambipolar silicon nanowire FinFETs. The low thermal budget processing, compatible with monolithic 3D device integration, makes use of low pressure chemical vapor deposition (LPCVD) of amorphous Si ...

Clock distribution networks are affected by different sources of variations. The resulting clock uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical model of skitter, which consists of clock skew and jitter ...

Universal quantum algorithms that prepare arbitrary n-qubit quantum states require O(2n) gate complexity. The complexity can be reduced by considering specific families of quantum states depending on the task at hand. In particular, multipartite quantum st ...

Giovanni De Micheli

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Synthesis of Predictable Networks-on-Chip Based Interconnect Architectures for Chip Multi-Processors

Memristor-Based Devices for Sensing

Biochips for Regenerative Medicine: Real-time Stem Cell Continuous Monitoring as Inferred by High-Throughput Gene Analysis

Method to manage the load of peripheral elements within a multicore system

Fully Integrated Biochip Platforms for Advanced Healthcare

Computationally Efficient Multiple-Independent-Gate Device Model

An Outlook on Design Technologies for Future Integrated Systems

A Low-Overhead Method for Pre-bond Test of Resonant 3-D Clock Distribution Networks

A Lightweight Cryptographic System for Implantable Biosensors

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains

Inexpensive 1024-Channel 3D Telesonography System on FPGA

SAT-Sweeping Enhanced for Logic Synthesis

Designing Application-Specific Networks on Chips with Floorplan Information

Area-Oriented Optimization After Standard-Cell Mapping

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits

Nano-Tera.CH: Nano-technologies for Tera-scale Problems

Ambipolar silicon nanowire FETs with stenciled-deposited metal gate

Timing Uncertainty in 3-D Clock Trees due to Process Variations and Power Supply Noise

Efficient Preparation of Cyclic Quantum States