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Giovanni De Micheli

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Related publications (554)

A Simulation Methodology for Reliability Analysis in Multi-Core SoCs

Yusuf Leblebici, Giovanni De Micheli, Ayse Kivilcim Coskun

Reliability has become a significant challenge for system design in new process technologies. Higher integration levels dramatically increase power densities, which leads to higher temperature and adverse effects on reliability. In this paper, we introduce ...

ACM Press2006

Bioimaging and Functional Genomics

Giovanni De Micheli, Luca Benini

For better understanding of genetic mechanisms underlying clinical observations, it is interesting to determine which genes and clinical traits are interrelated. In the last few years a consistent amount of research in genomics has been done concerning cor ...

2006

Reliability Support for On-chip Memories Using Networks-on-Chips

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. ...

2006

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

On-chip wires are becoming unreliable as the effect of various noise sources increases with technology scaling. This leads to unpredictable timing delay variations on the interconnect wires. There is a significant need to mitigate the effect of parasitics ...

2006

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips

Giovanni De Micheli, David Atienza Alonso, Federico Angiolini, Luca Benini, Srinivasan Murali

Networks on Chip (NoC) has emerged as the paradigm for designing scalable communication architecture for Systems on Chips (SoCs). Avoiding the conditions that can lead to deadlocks in the network is critical for using NoCs in real designs. Methods that can ...

2006

Analysis and Optimization of MPSoC Reliability

Yusuf Leblebici, Giovanni De Micheli, Ayse Kivilcim Coskun

Advancements in technology enable integration of multiple devices on a single core, resulting in increased on chip power and temperature densities. Higher temperatures, in turn, present a significant challenge for reliability. In this work we propose a com ...

2006

Routing Aware Switch Hardware Customization for Networks on Chips

Giovanni De Micheli, Srinivasan Murali

Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC wit ...

2006

Architectural Exploration of MPSoC Designs Based on an FPGA Emulation Framework

Giovanni De Micheli, David Atienza Alonso, Luca Benini, Pablo Garcia del Valle

With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are very complex to design as they must execute multiple co ...

2006

An Opportunistic Reconfiguration Strategy for Environmentally Powered Devices

Giovanni De Micheli, Alexandru Emilian Susu

Environmental energy is becoming a feasible alternative to traditional energy sources for ultra low-power devices such as sensor nodes and smart watches. Moreover, the increas- ing need for exibility and recon gurability of such devices makes its energy ma ...

2006

An Application-Specific Design Methodology for STbus Crossbar Generation

Giovanni De Micheli, Srinivasan Murali

As the communication requirements of current and future Multiprocessor Systems on Chips (MPSoCs) continue to increase, scalable communication architectures are needed to support the heavy communication demands of the system. This is reflected in the recent ...

2005

NoC Emulation on FPGA: HW/SW Synergy for NoC Features Exploration

Giovanni De Micheli, Nicolas Genko, David Atienza Alonso

Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. NoCs can have regular ...

2005

A Complete Network-On-Chip Emulation Framework

Giovanni De Micheli, Nicolas Genko, David Atienza Alonso, Roman Hermida Correa

Current systems-on-chip (SoC) execute applications that demand extensive parallel processing. Networks-on-chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoC can have regular ...

2005

A Novel Approach for Network on Chip Emulation

Giovanni De Micheli, Nicolas Genko, David Atienza Alonso, Luca Benini, Roman Hermida Correa

Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoCs can have regular or a ...

2005

A Robust Self-calibrating Transmission Scheme for On-Chip Networks

Paolo Ienne, Patrick Thiran, Frédéric Worm, Giovanni De Micheli

Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are i ...

2005

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