Pascal Andreas Meinerzhagen

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Related publications (24)

Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology

Pascal Andreas Meinerzhagen, Andreas Peter Burg

In this paper, standard-cell based memories (SCMs) are proposed as an alternative to full-custom sub-VT SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the ...

2011

Design and failure analysis of logic-compatible multilevel gain-cell-based DRAM for fault-tolerant VLSI systems

Pascal Andreas Meinerzhagen, Andreas Peter Burg

This paper considers the problem of increasing the storage density in fault-tolerant VLSI systems which require only limited data retention times. To this end, the concept of storing many bits per memory cell is applied to area-efficient and fully logic-co ...

ACM Press2011

Synthesis strategies for sub-VT systems

Pascal Andreas Meinerzhagen, Andreas Peter Burg, Oskar Andersson

Various synthesis strategies relying on conventional standard-cell libraries (SCLs) are evaluated in order to minimize the energy dissipation per operation in sub-threshold (sub-VT) systems. First, two sub-V T analysis methods are reviewed, both of which a ...

IEEE2011

A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

Pascal Andreas Meinerzhagen, Christoph Studer, Andreas Peter Burg

We present a low-power quasi-cyclic (QC) low density parity check (LDPC) decoder that meets the throughput requirements of the highest-rate (600 Mbps) modes of the IEEE 802.11n WLAN standard. The design is based on the layered offset-min-sum algorithm and ...

IEEE2010

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