Publications by Paolo Ienne | EPFL Graph Search

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Look-Up Tables (LUTs) are universally used in FPGAs as the elementary logic blocks. They can implement any logic function and thus covering a circuit is a relatively straightforward problem. Naturally, flexibility comes at a price, and increasing the number of LUT inputs to cover larger parts of a circuit has an exponential cost in the LUT complexity. Hence, rarely LUTs with more than 4-6 inputs have been used. In this paper we argue that other elementary logic blocks can provide a better compromise between

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

We introduce a compiler that automatically inserts software countermeasures to protect cryptographic algorithms against power-based side-channel attacks. The compiler first estimates which instruction instances leak the most information through side-channe ...

This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Extensions (ISEs). Way Stealing provides more bandwidth to the ISE-logic than the ...

High-level synthesis (HLS) helps to develop hard-ware accelerators for field-programmable gate arrays (FPGAs) using C/C++ descriptions. HLS is tailored to exploit instruction-level parallelism and, where available, data-level parallelism in applications. Y ...

The efficiency of spatial computing depends on the ability to achieve maximal parallelism. This necessitates memory interfaces that can correctly handle memory accesses that arrive in arbitrary order while still respecting data dependencies and ensuring ap ...

Circuits generated by dynamically scheduled high-level synthesis (HLS) outperform static counterparts when execution-dependent operation reordering is possible. A key opportunity are potential memory dependencies that static analysis cannot rule out: Statically scheduled circuits must assume a worst-case scenario, enforcing conservative in-order execution even when unnecessary. In contrast, dynamically scheduled circuits use load-store queues (LSQs) to detect access collisions at runtime and reorder accesse

Reconfigurable Systems-an-Chip (RSoCs) on the market consist of full -fledged processors and large Field -Programmable Gate Arrays (FPGAs). The latter can be used to implement the system glue logic, various peripherals, and application - specific coprocessors. Using FPGAs for application -specific coprocessors has certain speedup potentials, but it is less present in practice beca use of the complexity of interfacing the software application with the coprocessor. In the present application, we present a vir

The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementatio ...

Way Stealing is a simple architectural modification to a cache-based processor that increases the data bandwidth to and from application-specific instruction set extensions (ISEs), which increase performance and reduce energy consumption. Way Stealing offe ...

Task-level parallelism (TLP) is a long-standing approach in parallelizing control-dominated algorithms in software and has recently drawn interest in hardware acceleration thanks to the simplicity of managing tasks in hardware. Several TLP frameworks for FPGAs, like ParallelXL and HardCilk, leverage high-level synthesis to facilitate the acceleration of efficient TLP algorithms on FPGAs. In particular, HardCilk managed to efficiently deploy up to 256 processing elements (PEs) on a single FPGA system for mic

The increasing importance,of datapath circuits in complex systems-on-chip calls for special arithmetic optimizations. The goal is to automatically achieve the handcrafted results which escape classic logic optimizations. Some work has been done in the rece ...

Carry chains facilitate the implementation of adders and improve the performance of arithmetic circuits in FPGAs. The last version of the commonly used open-source Verilog-to-Routing (VTR) CAD flow now enables modelling carry chains in FPGA architectures. ...

Creating dataflow circuits with HLS tools to exploit memory- or task-level parallelism is challenging. These tools can generate functional designs easily, but optimizing them for performance often requires extensive code restructuring, pragma tuning, and even RTL integration. Writing low-level RTL, however, is rarely productive. We propose Chext, a domain-specific language that provides a thin abstraction layer over RTL for building complex dataflow circuits with elastic interfaces. Chext enables a safe and

String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...

Networks-on-Chip are emerging as a widely accepted alternative for the traditional bus architectures. However, their applicability by the system designers is far away from being intuitive due to their lack of predictability. This communication predictabili ...

Functional verification occupies a significant amount of the digital circuit design cycle. In this paper, we present a novel approach to improve circuit debugging which not only localizes errors with high confidence, but can also provide semantically-meani ...

Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have been widely used to implement a myriad of applications from different domains. As a result of their low-level hardware reconfigurability, FPGAs have much faster d ...

Embedded cryptographic systems, such as smart cards, require secure implementations that are robust to a variety of low-level attacks. Side-Channel Attacks (SCA) exploit the information such as power consumption, electromagnetic radiation and acoustic leak ...

FPGAs can provide high performance and energy efficiency to many applications; therefore, they are attractive computing platforms in a cloud environment. However, FPGA application development requires extensive hardware design knowledge which significantly ...

Paolo Ienne

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Rethinking FPGAs: Elude the Flexibility Excess of LUTs with And-Inverter Cones

Combining Dynamic & Static Scheduling in High-level Synthesis

Automatic Application of Power Analysis Countermeasures

Way Stealing: Cache-assisted Automatic Instruction Set Extensions

HardCilk: Cilk-like Task Parallelism for FPGAs

An Out-of-Order Load-Store Queue for Spatial Computing

Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS

Virtual Memory Window with Dynamic Prefetching Support

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions

NetCilk: Extending Task-Level Parallelism Seamlessly across FPGAs

Data-flow transformations to maximize the use of carry-save representation in arithmetic circuits

Improved carry chain mapping for the VTR flow

Chext: A Domain-specific Language for Safe and Agile Elastic Dataflow Accelerators

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

A Predictable Communication Scheme for Embedded Multiprocessor Systems

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction

Synthesizing General-Purpose Code Into Dynamically Scheduled Circuits

An Architecture-Independent Instruction Shuffler to Protect against Side-Channel Attacks

Designing a Virtual Runtime for FPGA Accelerators in the Cloud