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A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

Dynamically scheduled high-level synthesis can exploit high levels of parallelism in poorly-predictable control-dominated applications. Yet, dataflow circuits are often generated by literal conversion of basic blocks into circuits interconnected in such a ...

To reduce the average memory access time, most current processors make use of a multilevel cache subsystem. However, despite the proven benefits of such cache structures in the resulting throughput, conventional operations such as copy, simple maps and red ...

Many fundamental graph mining problems, such as maximal clique enumeration and subgraph isomorphism, can be solved using combinatorial algorithms that are naturally expressed in a recursive form. However, recursive graph mining algorithms suffer from a hig ...

Cycles are one of the fundamental subgraph patterns and being able to enumerate them in graphs enables important applications in a wide variety of fields, including finance, biology, chemistry, and network science. However, to enable cycle enumeration in r ...

Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are i ...

Shared Virtual Memory (SVM) is a mechanism that allows host-side applications and FPGA accelerators to access the same virtual address space. It enables accelerating algorithms with unpredictable memory access patterns by making transparent pointer sharing ...

This paper advocates the placement of Architecturally Visible Communication (AVC) buffers between adjacent cores in MPSoCs to provide high-throughput communication for streaming applications. Producer/consumer relationships map poorly onto cache-based MPSo ...

Hybrid flash storages combine a small Single-Level Cell (SLC) partition with a large Multilevel Cell (MLC) partition. Compared to MLC-only solutions, the SLC partition exploits fast and short local write updates, while the MLC part brings large capacity. O ...

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

Historically, hardware acceleration technologies have either been application-specific, therefore lacking in flexibility, or fully programmable, thereby suffering from notable inefficiencies on an application-by-application basis. To address the growing ne ...

FPGAs rely on massive datapath parallelism to accelerate applications even with a low clock frequency. However, applications such as sparse linear algebra and graph analytics have their throughput limited by irregular accesses to external memory for which ...

Soft and highly-customized processors are emerging as a common way to efficiently control large amount of computing resources available on FPGAs. Yet, some processor architectures of choice for DSP and media applications, such as wide-issue VLIW processors ...

String sorting is an important part of database and MapReduce applications; however, it has not been studied as extensively as sorting of fixed-length keys. Handling variable-length keys in hardware is challenging and it is no surprise that no string sorte ...

In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency a ...

Increased lower metal resistance makes physical aspects of Field-Programmable Gate Array (FPGA) switch-blocks more relevant than before. The need to navigate a design space where each individual switch can have significant impact on the FPGA's performance ...

The main goal of this paper is to expose the community to past achievements and future possible uses of Instruction Set Extension (ISE) in security applications. Processor customization has proven to be an effective way for achieving high performance with ...

This repository contains the source code, benchmarks, and experimental results associated with the paper "Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS" by Rouzbeh Pirayadi (EPFL), Ayatallah Elakhras (EPFL), Mirjana Stojilović (EPFL), and Paolo Ienne (EPFL). The paper has been accepted for publication in the Proceedings of the 34th International Symposium on Field-Programmable Gate Arrays (ISFPGA 2026). Abstract: Circuits generated by dynamically scheduled high-level synthesis

Several techniques have been proposed for automatically searching for FPGA switch-blocks which typically show some tangible advantage over the well-known academic architectures. However, the resulting switch-blocks usually exhibit high levels of irregulari ...

For efficient acceleration on FPGA, it is essential for external memory to match the throughput of the processing pipelines. However, the usable DRAM bandwidth decreases significantly if the access pattern causes frequent row conflicts. Memory controllers ...

Paolo Ienne

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DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits

Exploiting Compute Caches for Memory Bound Vector Operations

Parallelizing Maximal Clique Enumeration on Modern Manycore Processors

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

A Robust Self-calibrating Transmission Scheme for On-Chip Networks

FlexiMem: Flexible Shared Virtual Memory for PCIe-attached FPGAs

MPSoC Design using Application-Specific Architecturally Visible Communication

Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash

From C/C plus plus Code to High-Performance Dataflow Circuits

Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

Making Wide-Issue VLIW Processors Viable on FPGAs

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort

An Accelerator for High Efficient Vision Processing

Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns

Instruction Set Extensions for Secure Applications

Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS

Regularity Matters: Designing Practical FPGA Switch-Blocks

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA