Lectures related to Combinatorial Logic Circuits

Explains the full adder's role in binary addition and its design using transistors.

Explores Boolean algebra properties and optimization techniques using Karnaugh diagrams and De Morgan's theorems.

Covers the Logical Effort method for optimizing logic delay and gate sizing impact.

Covers the Shockley MOS transistor model, CMOS logic gates, transistor operation, design parameters, and I-V characteristics.

Covers abstraction levels, EPFL design flow, lowerbounds, and layout recommendations.