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Lecture

VHDL Packages

In course

EE-334: Digital systems design

Students will acquire basic knowledge about methodologies and tools for the design, optimization, and verification of custom digital systems/hardware. They learn how to design synchronous digital circuits on register transfer level, analyse their timing a ...

Description

This lecture explains the importance of VHDL packages, which are collections of reusable elements used in VHDL designs. The instructor covers the benefits of using packages, such as simplifying design consistency, minimizing errors, and facilitating changes across multiple design elements. The lecture also touches on the use of packages to define constants, components, data types, functions, and procedures in VHDL. Additionally, the instructor provides insights on how to include packages in designs, the role of libraries in VHDL, and the process of using packages from libraries. The lecture concludes with practical examples of using packages in designing VHDL circuits and the advantages of organizing constants in packages for better design management.

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Instructor

Andreas Peter Burg

Andreas Burg was born in Munich, Germany, in 1975. He received his Dipl.-Ing. degree in 2000 from the Swiss Federal Institute of Technology (ETH) Zurich, Zurich, Switzerland. He then joined the Integrated Systems Laboratory of ETH Zurich, from where he graduated with the Dr. sc. techn. degree in 2006. In 1998, he worked at Siemens Semiconductors, San Jose, CA. During his doctoral studies, he was an intern with Bell Labs Wireless Research for a total of one year. From 2006 to 2007, he held positions as postdoctoral researcher at the Integrated Systems Laboratory and at the Communication Theory Group of the ETH Zurich. In 2007 he co-founded Celestrius, an ETH-spinoff in the field of MIMO wireless communication, where he was responsible for the ASIC development as Director for VLSI. In January 2009, he joined ETH Zurich as SNF Assistant Professor and as head of the Signal Processing Circuits and Systems group at the Integrated Systems Laboratory. In January 2011, he became a Tenure Track Assistant Professor at the Ecole Polytechnique Federale de Lausanne (EPFL) where he is leading the Telecommunications Circuits Laboratory in the School of Engineering. In June 2018 he was promoted to the role of a Tenured Associate Professor. In 2000, Mr. Burg received the Willi Studer Award and the ETH Medal for his diploma and his diploma thesis, respectively. Mr. Burg was also awarded an ETH Medal for his Ph.D. dissertation in 2006. In 2008, he received a 4-years grant from the Swiss National Science Foundation (SNF) for an SNF Assistant Professorship. In his professional career, Mr. Burg was involved in the development of more than 25 ASICs. He is a member of the IEEE and of the European Association for Signal Processing (EURASIP). Research interests and expertise

Circuits and systems for telecommunications (wireless and wired)
Prototyping and silicon implementation of new communication technologies
Development of communication algorithms and optimization for hardware implementation
Low-power VLSI signal processing for communications and other applications
Digital integrated circuits
Circuits for image and video processing

Official source

Related concepts (10)

VHDL

The VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gates, for design entry, documentation, and verification purposes. Since 1987, VHDL has been standardized by the Institute of Electrical and Electronics Engineers (IEEE) as IEEE Std 1076; the latest version of which is IEEE Std 1076-2019.

Accellera

Accellera Systems Initiative (Accellera) is a standards organization that supports a mix of user and vendor standards and open interfaces development in the area of electronic design automation (EDA) and integrated circuit (IC) design and manufacturing. It is less constrained than the Institute of Electrical and Electronics Engineers (IEEE) and is therefore the starting place for many standards. Once mature and adopted by the broader community, the standards are usually transferred to the IEEE.

Packaging and labeling

Packaging is the science, art and technology of enclosing or protecting products for distribution, storage, sale, and use. Packaging also refers to the process of designing, evaluating, and producing packages. Packaging can be described as a coordinated system of preparing goods for transport, warehousing, logistics, sale, and end use. Packaging contains, protects, preserves, transports, informs, and sells. In many countries it is fully integrated into government, business, institutional, industrial, and personal use.

Hardware description language

In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits. A hardware description language enables a precise, formal description of an electronic circuit that allows for the automated analysis and simulation of an electronic circuit.

C to HDL

C to HDL tools convert C language or C-like computer code into a hardware description language (HDL) such as VHDL or Verilog. The converted code can then be synthesized and translated into a hardware device such as a field-programmable gate array. Compared to software, equivalent designs in hardware consume less power (yielding higher performance per watt) and execute faster with lower latency, more parallelism and higher throughput.

Related lectures (26)

Introduction au VHDL

Covers VHDL basic concepts, program structure, objects, types, operators, literals, and arrays.

Sequential Logic Circuits in VHDL

Covers modeling sequential logic circuits in VHDL, including processes, control instructions, flip-flops, counters, and registers.

Concurrent Instructions in VHDL

Covers concurrent instructions in VHDL, demonstrating parallel processing and conditional assignments.

Parallel Port & Nios II Interrupts

Covers the design of a programmable parallel port interface for an Avalon bus and the architecture of the Nios II processor.

High-Level Synthesis: Formally Verified Elastic Circuits