Explores Finite State Machines (FSMs) in digital system design, covering Mealy and Moore FSMs, state diagrams, VHDL implementation, and state encoding.
Covers the implementation and verification of encoder and decoder for prefix-free codes, including classes and types, lemmas on trees, and the main theorem.
Explores the foundations of modular verification using Separation Logic for realistic concurrent programs and discusses the challenges of shared mutable state in concurrency.
Explores real-time control systems, determinism, and automation in critical systems, emphasizing the significance of meeting time constraints for safety and efficiency.