Mediaspace scheduled maintenance: Aug 25, 2026 07:00 - 12:00 AM. During this time, videos will be temporarily unavailable. Check status updates.

Graph
Search

Course

CS-472: Design technologies for integrated systems

Summary

Hardware compilation is the process of transforming specialized hardware description languages into circuit descriptions, which are iteratively refined, detailed and optimized. The course presents algorithms, tools and methods for hardware compilation and logic synthesis.

Lectures

Instructors (3)

Giovanni De Micheli

Pasquale Davide Schiavone

David Mallasen Quintana

Official source

https://edu.epfl.ch/coursebook/en/design-technologies-for-integrated-systems-CS-472

Moodle Page

http://go.epfl.ch/CS-472

About this result

This page is automatically generated and may contain information that is not correct, complete, up-to-date, or relevant to your search query. The same applies to every other page on this website. Please make sure to verify the information with EPFL's official sources.

Summary

Lectures

Instructors (3)

Giovanni De Micheli

Pasquale Davide Schiavone

David Mallasen Quintana

Official source

https://edu.epfl.ch/coursebook/en/design-technologies-for-integrated-systems-CS-472

Moodle Page

http://go.epfl.ch/CS-472

About this result

Ontological neighbourhood

Computer engineering

Hardware engineering: Application-specific integrated circuit

Lectures in this course (8)

Synchronous Logic Circuits: Modeling and Optimization Log in to Mediaspace to watch this video

Explores synchronous logic circuits, state-based modeling, optimization techniques, and finite-state machine state minimization.

Sequential Circuits: Optimization and Retiming Log in to Mediaspace to watch this video

Covers structural models, synthesis approaches, and retiming techniques for sequential circuits.

Relaxation-based Retiming Log in to Mediaspace to watch this video

Covers relaxation-based retiming to optimize cycle-time by shortening paths with excessive delays.

Boolean Optimization: MIGs and Majority Gates Log in to Mediaspace to watch this video

Explores Boolean function optimization using Majority-Inverter Graphs and Majority Gates, including algebraic rules and exact synthesis.

Timing Verification and Optimization Log in to Mediaspace to watch this video

Covers timing verification, gate delay modeling, network delay, sensitizable paths, and critical path analysis in digital circuits.

Related courses (32)

EE-334: Digital systems design

Students will acquire basic knowledge about methodologies and tools for the design, optimization, and verification of custom digital systems/hardware. They learn how to design synchronous digital circuits on register transfer level, analyse their timing a ...

CS-471: Advanced multiprocessor architecture

Multiprocessors are basic building blocks for all computer systems. This course covers the architecture and organization of modern multiprocessors, prevalent accelerators (e.g., GPU, TPU), and datacenters. It includes a research project on multiprocessors ...

CS-173: Fundamentals of digital systems

Welcome to the introductory course in digital design and computer architecture. In this course, we will embark on a journey into the world of digital systems, exploring the fundamental principles and concepts that underpin modern computing technology. ...

EE-110: Logic systems (for MT)

Ce cours couvre les fondements des systèmes numériques. Sur la base d'algèbre Booléenne et de circuitscombinatoires et séquentiels incluant les machines d'états finis, les methodes d'analyse et de synthèse de systèmelogiques sont étudiées et appliquée ...

EE-330: Digital IC design

Digital IC Design presents the fundamentals of digital integrated circuit design. The methods and techniques aiming at the fabrication and development of digital integrated circuits are reviewed, the major design style pertaining to digital logic and memor ...