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Related publications (28)

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Reconfigurable Logic Gates Based on Programable Multistable Mechanisms

Simon Nessim Henein, Ilan Vardi, Hubert Pierre-Marie Benoît Schneegans, Mohamed Gamal Abdelrahman Ahmed Zanaty

Binary logic gates are building blocks of computing machines, in particular, electronic computers. One variant is the programable logic gate, also known as the reconfigurable logic gate, in which the logical function implemented can be modified. In this pa ...

2020

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Andrea Bonetti

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling ...

EPFL2019

End-to-End Industrial Study of Retiming

Giovanni De Micheli, Cunxi Yu

Sequential circuits are combinational circuits that are separated by registers. Retiming is considered as the most promising technique for optimizing sequential circuits, that involves moving the edge-triggered registers across the combinational logic with ...

IEEE2018

Improvements to Boolean resynthesis

Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù

In electronic design automation Boolean resynthesis techniques are increasingly used to improve the quality of results where algebraic methods hit local minima Boolean methods rely on complete functional properties of a logic circuit, preferably including ...

IEEE2018

Design techniques for a stable operation of cryogenic field-programmable gate arrays

Edoardo Charbon

In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires ...

2018

Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers

Cunxi Yu

The paper presents a novel method to verify and debug gate-level arithmetic circuits implemented in Galois Field arithmetic. The method is based on forward reduction of the specification polynomials of the circuit in GF(2(m)) using GF(2) models of its logi ...

IEEE2018

Area and Power Efficient Ultra-Wideband Transmitter Based on Active Inductor

Catherine Dehollain, Franco Maloberti, Kerim Türe, Arnout Jan J Devos

This paper presents the design of an impulse radio ultra-wideband (IR-UWB) transmitter for low-power, short-range, and high-data rate applications such as high density neural recording interfaces. The IR-UWB transmitter pulses are generated by modulating t ...

2018

Characterization of a 9-Decade Femtoampere ASIC Front-End for Radiation Monitoring

Maher Kayal, François Krummenacher, Evgenia Voulgari

An ultra-low current sensing digitizer circuit was designed for radiation monitoring for personnel and environmental safety at CERN. The Ultralow Picoammeter 2 (Utopia 2) ASIC includes some key functionalities like on-chip active leakage current compensati ...

2018