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Concept

32-bit computing

Related publications (19)

Programmable Seizure Detector Using a 32-bit RISC Processor for Implantable Medical Devices

Alexandre Schmid, Keyvan Farhang Razi

A programmable patient-customized epileptic seizure detector is proposed in this paper to enable neurologists and patients to have constructive interactions with the implantable medical device. The programmability feature is enabled by designing a low-powe ...

IEEE2023

A 3.3-Gb/s SPAD-Based Quantum Random Number Generator

Edoardo Charbon, Francesco Gramuglia, Pouyan Keshavarzian

Quantum random number generators (QRNGs) are a burgeoning technology used for a variety of applications, including modern security and encryption systems. Typical methods exploit an entropy source combined with an extraction or bit generation circuit in or ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

Anonymous Tokens with Stronger Metadata Bit Hiding from Algebraic MACs

Serge Vaudenay, Fatma Betül Durak

On the one hand, the web needs to be secured from malicious activities such as bots or DoS attacks; on the other hand, such needs ideally should not justify services tracking people's activities on the web. Anonymous tokens provide a nice tradeoff between ...

2023

Full key recovery side-channel attack against ephemeral SIKE on the Cortex-M4

Aymeric Genet, Novak Kaluderovic

This paper describes the first practical single-trace side-channel power analysis of SIKE. While SIKE is a post-quantum key exchange, the scheme still relies on a secret elliptic curve scalar multiplication which involves a loop of a double-and-add procedu ...

2021

Write Termination circuits for RRAM : A Holistic Approach From Technology to Application Considerations

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Marco Antonio Rios

While Resistive Random Access Memories (RRAM) are perceived nowadays as a promising solution for the future of computing, these technologies suffer from intrinsic variability regarding programming voltage, switching speed and achieved resistance values. Wr ...

IEEE2020

A Fast, Reliable and Wide-voltage-range In-memory Computing Architecture

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, William Andrew Simon

In-Memory Computing (IMC) solutions, and particularly bitline computing in SRAM, appear promising as they mitigate one of the most energy consuming aspects in computation: data movement. In this work we propose a fast (2.4Ghz for bitwise operations and 2.4 ...

Association for Computing Machinery2019

Adaptive simulation-based framework for error characterization of inexact circuits

Vincent Frédéric Camus

To design faster and more energy-efficient systems, numerous inexact arithmetic operators have been proposed, generally obtained by modifying the logic structure of conventional circuits. However, as the quality of service of an application has to be ensur ...

PERGAMON-ELSEVIER SCIENCE LTD2019

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor

Mihai Adrian Ionescu, Josef Andreas Schuler, Wolfgang Amadeus Vitale, Anna Krammer, Emanuele Andrea Casu, Arnab Biswas, Cem Alper, Teodor Rosca

Steep-slope transistors allow to scale down the supply voltage and the energy per computed bit of information as compared to conventional field-effect transistors (FETs), due to their sub-60 mV/decade subthreshold swing at room temperature. Currently pursu ...

Nature Research2017

Some Cryptanalytic Results on Lizard

Subhadeep Banik

Lizard is a lightweight stream cipher proposed by Hamann, Krause and Meier in IACR ToSC 2017. It has a Grain-like structure with two state registers of size 90 and 31 bits. The cipher uses a 120 bit secret key and a 64 bit IV. The authors claim that Lizard ...

2017

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Jeremy Hugues-Felix Constantin, Thomas Christoph Müller, Lorenz Flavio Schmid

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

Sound reasoning about integral data types with a reusable SMT solver interface

Viktor Kuncak, Régis William Blanc

We extend the Leon verification system for Scala with support for bit-vector reasoning, thus addressing one of its fundamental soundness limitation with respect to the treatment of integers primitives. We leverage significant progresses recently achieved i ...

ACM Press2015

Improved Linear Cryptanalysis of Reduced-Round MIBS

Serge Vaudenay, Asli Bay, Jialin Huang

MIBS is a 32-round lightweight block cipher with 64-bit block size and two different key sizes, namely 64-bit and 80-bit keys. Bay et al. provided the first impossible differential, differential and linear cryptanalyses of MIBS. Their best attack was a lin ...

Springer2014

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

Yusuf Leblebici, Alessandro Cevrero, Michail Zervas, Yüksel Temiz, Giulia Beanato, Panagiotis Athanasopoulos, Paolo Giovannini

An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by through-silicon-vias (TSVs). Each die features four 32-bit embedded processors and associated m ...

2012

A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-Vt) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforwar ...

2012

Why Nothing Matters: The Impact of Zeroing

Memory safety defends against inadvertent and malicious misuse of memory that may compromise program correctness and security. A critical element of memory safety is zero initialization. The direct cost of zero initialization is surprisingly high: up to 12 ...

2011

Fast Software AES Encryption

Joppe Willem Bos, Dag Arne Osvik

This paper presents new software speed records for AES-128 encryption for architectures at both ends of the performance spectrum. On the one side we target the low-end 8-bit AVR rnicrocontrollers and 32-bit ARM microprocessors, while on the other side of t ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

Bit Precision Analysis for Compressed Sensing

Mohammad Amin Shokrollahi, Mahdi Cheraghchi Bashi Astaneh

This paper studies the stability of some reconstruction algorithms for compressed sensing in terms of the bit precision. Considering the fact that practical digital systems deal with discretized signals, we motivate the importance of the total number of ac ...

2009

Multi-bit error tolerant caches using two-dimensional error coding

Babak Falsafi

In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses, soft and hard errors in the memory system will increase and single error ev ...

2007

High resolution miniature rotary microactuator

Jean-Marc Breguet

For the development of high precision mobile microrobots with a size of about one cm3, capable of micromanipulation tasks, small and precise actuators have to be developed in order to provide the microrobot and its manipulation tools with the required degr ...

2004