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AMD APU

Related publications (19)

Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads

David Atienza Alonso, Marina Zapater Sancho, Darong Huang, Luis Maria Costero Valero, Qunyou Liu

The increasing demand for computing power and the emergence of heterogeneous computing architectures have driven the exploration of innovative techniques to address current limitations in both the compute and memory subsystems. One such solution is the use ...

2024

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Aurélien François Gilbert Bloch

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

EPFL2023

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Dataflow programming is a methodology that enables the development of high-level, parametric programs that are independent of the underlying platform. This approach is particularly useful for heterogeneous platforms, as it eliminates the need to rewrite ap ...

SPRINGER2023

Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Developing and fine-tuning software programs for heterogeneous hardware such as CPU/GPU processing platforms comprise a highly complex endeavor that demands considerable time and effort of software engineers and requires evaluating various fundamental comp ...

MDPI2022

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Writing and optimizing application software for heterogeneous platforms including GPU units is a very difficult task that requires designer efforts and resources to consider several key elements to obtain good performance. Dataflow programming has shown to ...

2022

Programming Heterogeneous CPU-GPU Systems by High-Level Dataflow Synthesis

Marco Mattavelli, Endri Bezati, Aurélien François Gilbert Bloch

Heterogeneous processing platforms combining in various architectures CPUs, GPUs, and programmable logic, are continuously evolving providing at each generation higher theoretical levels of computing performance. However, the challenge of how efficiently s ...

IEEE2020

GPU-accelerated data management under the test of time

Anastasia Ailamaki, Periklis Chrysogelos, Angelos Christos Anadiotis, Panagiotis Sioulas, Syed Mohammad Aunn Raza

GPUs are becoming increasingly popular in large scale data center installations due to their strong, embarrassingly parallel, processing capabilities. Data management systems are riding the wave by using GPUs to accelerate query execution, mainly for analy ...

2020

Trading off Energy versus Accuracy in Modern Computing Systems : From Digital Circuit Design to Programming Techniques

Jérémy Lucien Maurice Schlachter

The slowdown of Moore's law, which has been the driving force of the electronics industry over the last 5 decades, is causing serious problem to Integrated Circuits (ICs) improvements. Technology scaling is becoming more and more complex and fabrication co ...

EPFL2018

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Andrea Bonetti, Adam Shmuel Teman, Jeremy Hugues-Felix Constantin, Thomas Christoph Müller, Lorenz Flavio Schmid

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

Sub-electron CIS noise analysis in 65 nm process

Christian Enz, Assim Boukhayma, Raffaele Capoccia

For a 4T pixel-based CMOS image sensors (CIS) readout chain, with column-level amplification and CDS, we show that the input-referred total noise in a standard 65 nm process can be reduced to 0.37 e-rms. Based on transient noise simulation using Eldo, the ...

2016

Stabilization of electrodynamic bearings with active magnetic dampers

Qingwen Cui

Electrodynamic Bearings (EDBs) are a kind of passive magnetic bearings that exploits the interaction between the induced eddy currents in a conductor and a magnetic field to provide re-storing forces. They have been regarded as an appealing alternative to ...

EPFL2016

Characterization of the Impact of Hardware Islands on OLTP

Anastasia Ailamaki, Pinar Tözün, Ippokratis Pandis, Danica Porobic, Miguel Sérgio De Oliveira Branco

Modern hardware is abundantly parallel and increasingly heterogeneous. The numerous processing cores have non-uniform access latencies to the main memory and processor caches, which causes variability in the communication costs. Unfortunately, database sys ...

Springer Verlag2016

GPU Acceleration for Simulating Massively Parallel Many-Core Platforms

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

Emerging massively parallel architectures such as a general-purpose processor plus many-core programmable accelerators are creating an increasing demand for novel methods to perform their architectural simulation. Most state-of-the-art simulation technolog ...

Institute of Electrical and Electronics Engineers2015

Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing

David Atienza Alonso, Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Ahmed Yasir Dogan

A multi-core architecture with ultra-low power consumption is needed for a wide variety of applications, especially in the bio-medical domain. In this patent, an ultra-low power multi-core architecture is presented: it is composed of one or more cores, sev ...

2014

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

Georgios Karakonstantis

In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped p ...

Elsevier2014

Complement Factor B Polymorphism and the Phenotype of Early Age-related Macular Degeneration

Purpose: Age-related macular degeneration (AMD) has been associated with a number of polymorphisms in genes in the complement pathway. We examined the potential genotype-phenotype correlation of complement factor B (CFB) (R32Q) polymorphisms in Caucasian p ...

Informa Healthcare2014

SIMinG-1k: A thousand-core simulator running on general-purpose graphical processing units

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

This paper introduces SIMinG-1k-a manycore simulator infrastructure. SIMinG-1k is a graphics processing unit accelerated, parallel simulator for design-space exploration of large-scale manycore systems. It features an optimal trade-off between modeling acc ...

Wiley-Blackwell2013

Analysis of the BN-600 fast-spectrum core mock-up at BFS-2 zero-power facility using MCNPX

Alessandro Marinoni, Konstantin Mikityuk, Gaëtan Girardin

A 3D full-core heterogeneous model of the BFS-62-3A critical benchmark experiment was developed and validated using the Monte Carlo MCNPX-2.4.0 code. ...

Elsevier2012

OLTP on Hardware Islands

Anastasia Ailamaki, Ippokratis Pandis, Danica Porobic, Pinar Tözün, Miguel Sérgio De Oliveira Branco

Modern hardware is abundantly parallel and increasingly heterogeneous. The numerous processing cores have non-uniform access latencies to the main memory and to the processor caches, which causes variability in the communication costs. Unfortunately, datab ...

2012