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Concept

Verilog

Related publications (26)

Hardware-in-the-Loop Validation of an FPGA-Based Real-Time Simulator for Power Electronics Applications

Farhad Rachidi-Haeri, Mario Paolone, Reza Razzaghi

This paper presents the hardware-in-the-loop (HIL) validation of a proposed FPGA-based real-time simulator for power electronics applications. The proposed FPGA-based real-time simulation platform integrates the Modified Nodal Analysis (MNA) method, Fixed ...

ipst.org2015

High-level synthesis of dataflow programs for heterogeneous platforms : design flow tools and design space exploration

Endri Bezati

The growing complexity of digital signal processing applications implemented in programmable logic and embedded processors make a compelling case the use of high-level methodologies for their design and implementation. Past research has shown that for comp ...

EPFL2015

TSPC Flip-Flop Circuit Design with Three-Independent-Gate Silicon Nanowire FETs

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Jian Zhang

True Single-Phase Clock (TSPC) Flip-Flops, based on dynamic logic implementation, are area-saving and high-speed compared to standard static flip-flops. Furthermore, logic gates can be embedded into TSPC flip-flops which significantly improves performance. ...

IEEE2014

Automatic Synthesis of Out-of-Core Algorithms

Viktor Kuncak, Christoph Koch, Ioannis Klonatos, Andres Nötzli, Andrej Spielmann

We present a system for the automatic synthesis of efficient algorithms specialized for a particular memory hierarchy and a set of storage devices. The developer provides two independent inputs: 1) an algorithm that ignores memory hierarchy and external st ...

ACM Press2013

Interpolation for Synthesis on Unbounded Domains

Viktor Kuncak, Régis William Blanc

Synthesis procedures compile relational specifications into functions. In addition to bounded domains, synthesis procedures are applicable to domains such as mathematical integers, where the domain and range of relations and synthesized code is unbounded. ...

Ieee2013

Process/Design Co-optimization of Regular Logic Tiles for Double-Gate Silicon Nanowire Transistors

Giovanni De Micheli, Yusuf Leblebici, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon, Shashi Kanth Bobba, Jian Zhang, Michele De Marchi

Ambipolar transistors with on-line configurability to n-type and p-type polarity are desirable for future integrated circuits. Regular logic tiles have been recognized as an efficient layout fabric for ambipolar devices. In this work, we present a process/ ...

2012