Cache control instruction

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All-pairs shortest paths (APSP) remains a major bottleneck for large-scale graph analytics, as data movement with cubic complexity overwhelms the bandwidth of conventional memory hierarchies. We propose RAPID-Graph, a processing-in-memory (PIM) system co-designed across algorithm, architecture, and device levels to address this challenge. At the algorithm level, we introduce a recursion-aware partitioner that enables an exact APSP computation by decomposing graphs into vertex tiles to reduce data dependency

Cloud platforms are increasingly relied upon to host diverse, resource-intensive workloads due to their scalability, flexibility, and cost-efficiency. In multi-tenant cloud environments, virtual machines are consolidated on shared physical servers to improve resource utilization. While virtualization guarantees resource partitioning for CPU, memory, and storage, it cannot ensure performance isolation. Competition for shared resources such as last-level cache, memory bandwidth, and network interfaces often l

Diffusion models achieve state-of-the-art video generation quality, but their inference remains expensive due to the large number of sequential denoising steps. This has motivated a growing line of research on accelerating diffusion inference. Among training-free acceleration methods, caching reduces computation by reusing previously computed model outputs across timesteps. Existing caching methods rely on heuristic criteria to choose cache/reuse timesteps and require extensive tuning. We address this limit

Transformers have revolutionized AI in natural language processing and computer vision, but their enormous computation and memory demands pose significant challenges for hardware acceleration. In practice, endto-end throughput is often limited by paged data movement and interconnect bandwidth, not just raw MAC count. This work proposes a unified system-accelerator co-design approach to efficiently accelerate transformer inference by jointly optimizing a novel hardware matrix accelerator and its system integ

Widespread adoption of deep neural networks (DNNs), coupled with the trillion-parameter scale of modern models, has pushed compute, memory, and power demands of training and inference to their limits, making DNN compression optimization essential for continued AI progress. Microscaling numerical formats have recently emerged as a powerful approach for low-precision training and inference, using block-wise representations that share an exponent across small groups of low-bitwidth elements. This thesis studie

Modern data-driven applications expose limitations of von Neumann architectures-extensive data movement, low throughput, and poor energy efficiency. Accelerators improve performance but lack flexibility and require data transfers. Existing compute in- and nearmemory solutions mitigate these issues but face usability challenges due to data placement constraints. We propose a novel cache architecture that doubles as a tightly-coupled compute-near-memory coprocessor. Our RISC-V cache controller executes custom

Server CPUs in the cloud have inherited their core microarchitecture from the desktop and mobile world, with performance primarily measured by single-core IPC. Furthermore, cores are integrated with large cache hierarchies within sockets and rely heavily on these caches to contain chip power envelopes, with little consideration given to utilization by workloads. Wasted silicon impacts both operational and embodied emissions in server platforms. In this work, we measure and compare silicon efficiency measure

Can Transformers predict new syllogisms by composing established ones? More generally, what type of targets can be learned by such models from scratch? Recent works show that Transformers can be Turing-complete in terms of expressivity, but this does not address the learnability objective. This paper puts forward the notion of globality degree of a target distribution to capture when weak learning is efficiently achievable by regular Transformers. This measure shows a contrast with the expressivity results

Analytical engines rely on in-memory caching to avoid disk accesses and provide timely responses by keeping the most frequently accessed data in memory. Purely frequency- & time-based caching decisions, however, are a proxy of the expected query execution ...

The automatic design of well-performing robotic controllers is still an unsolved problem due to the inherently large parameter space and noisy, often hard-to-define performance metrics, especially when sequential tasks need to be accomplished. Distal contr ...

Virtual memory (VM) is critical to the usability and programmability of hardware accelerators. Unfortunately, implementing accelerator VM efficiently is challenging because the area and power constraints make it difficult to employ the large multi-level TLBs used in general-purpose CPUs. Recent research proposals advocate a number of restrictions on virtual-to-physical address mappings in order to reduce the TLB size or increase its reach. However, such restrictions are unattractive because they forgo many

Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bottleneck for future GPUs due to long access latency, high power consumption, ...

Data management systems enable various influential applications from high-performance online services (e.g., social networks like Twitter and Facebook or financial markets) to big data analytics (e.g., scientific exploration, sensor networks, business intelligence). As a result, data management systems have been one of the main drivers for innovations in the database and computer architecture communities for several decades. Recent hardware trends require software to take advantage of the abundant paralleli

Ever-increasing amounts of data captured with rapid rise in a variety of applications analyzing that data fuel the steady development of data management systems. Modern hardware offers increasing core counts, faster memories, and network interfaces, however, the changes in hardware architectures prevent software systems from automatically benefiting from hardware innovation. In this book, we set out to survey the challenges posed by modern multicore processors to data management software that prevent it fro

The latency of memory access times is hence non-uniform, because it depends on where the request originates and where it is destined to go. Such systems are referred to as nonuniform memory access (or NUMA). Current x86 NUMA systems are cache coherent (cal ...

Cache control instruction

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RAPID-Graph: Recursive All-Pairs Shortest Paths Using Processing-in-Memory for Dynamic Programming on Graphs

CloudFormer: An Attention-Based Performance Prediction for Public Clouds with Unknown Workload

SenCache: Accelerating Diffusion Model Inference via Sensitivity-Aware Caching

Mitigating the Bandwidth Wall via Data-Streaming System-Accelerator Co-Design

Compressing DNNs Using Microscaling Formats with Sensitivity and Sparsity

ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions

Silicon Efficiency in Post-Moore Servers

How Far Can Transformers Reason? the Globality Barrier and Inductive Scratchpad

HPCache: Memory-Efficient OLAP Through Proportional Caching

A Noise-Resistant Mixed-Discrete Particle Swarm Optimization Algorithm for the Automatic Design of Robotic Controllers

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching

Databases on Modern Hardware

Databases on Modern Hardware. Summary

Challenges of Memory Management on Modern NUMA Systems