Concept

Symmetric multiprocessing

Related publications (27)

Secure Interface Design Leveraging Hardware/Software Support

Computer systems rely heavily on abstraction to manage the exponential growth of complexity across hardware and software. Due to practical considerations of compatibility between components of these complex systems across generations, developers have favou ...

EPFL2024

Dynamically crossing diabolic points while encircling exceptional curves: A programmable symmetric-asymmetric multimode switch

Fabrizio Minganti

Nontrivial spectral properties of non-Hermitian systems can lead to intriguing effects with no counterparts in Hermitian systems. For instance, in a two-mode photonic system, by dynamically winding around an exceptional point (EP) a controlled asymmetric-s ...

Nature Portfolio2023

Latency Interfaces for Systems Code

Rishabh Ramesh Iyer

This thesis demonstrates that it is feasible for systems code to expose a latency interface that describes its latency and related side effects for all inputs, just like the code's semantic interface describes its functionality and related side effects. S ...

EPFL2023

Massively parallel nodal discontinous Galerkin finite element method simulator for room acoustics

Jan Sickmann Hesthaven

We present a massively parallel and scalable nodal discontinuous Galerkin finite element method (DGFEM) solver for the time-domain linearized acoustic wave equations. The solver is implemented using the libParanumal finite element framework with extensions ...

Sage Publications Ltd2023

Reinforcement Learning-Based Joint Reliability and Performance Optimization for Hybrid-Cache Computing Servers

David Atienza Alonso, Marina Zapater Sancho, Ali Pahlevan, Darong Huang, Luis Maria Costero Valero

Computing servers play a key role in the development and process of emerging compute-intensive applications in recent years. However, they need to operate efficiently from an energy perspective viewpoint, while maximizing the performance and lifetime of th ...

2022

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

Paolo Ienne, Mikhail Asiatici

String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...

SPRINGER2021

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Philip Brisk, Mirjana Stojilovic

RePlAce is a state-of-the-art prototype of a flat, analytic, and nonlinear global cell placement algorithm, which models a placement instance as an electrostatic system with positively charged objects. It can handle large-scale standard-cell and mixed-cell ...

IEEE2020

Reconfigurable and Latchable Shape‐Morphing Dielectric Elastomers Based on Local Stiffness Modulation

Herbert Shea, Bekir Aksoy

Programmable soft materials exhibiting dynamically reconfigurable, reversible, fast, and latchable shape transformation are key for applications ranging from wearable tactile actuators to deployable soft robots. Multimorph soft actuator sheets with high lo ...

2020

Asynchronous Branch-Paralle Simulation of Detailed Neuron Models

Felix Schürmann

Simulations of electrical activity of networks of morphologically detailed neuron models allow for a better understanding of the brain. State-of-the-art simulations describe the dynamics of ionic currents and biochemical processes within branching topologi ...

2019

Functionality Enhanced Memories for Edge-AI Embedded Systems

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Pierre-Emmanuel Julien Marc Gaillardon, Marco Antonio Rios, William Andrew Simon

With the surge in complexity of edge workloads, it appeared in the scientific community that such workloads cannot be anymore overflown to the cloud due to the huge edge device to server communication energy cost and the high energy consumption induced in ...

IEEE2019

SMoTherSpectre: Exploiting Speculative Execution through Port Contention

Babak Falsafi, Mathias Josef Payer, Atri Bhattacharyya

Spectre, Meltdown, and related attacks have demonstrated that kernels, hypervisors, trusted execution environments, and browsers are prone to information disclosure through micro-architectural weaknesses. However, it remains unclear as to what extent other ...

ACM2019

Asynchronous Simulation of Neuronal Activity

Bruno Ricardo Da Cunha Magalhães

Simulations of the electrical activity of networks of morphologically-detailed neuron models allow for a better understanding of the brain. Short time to solution is critical in order to study long biological processes such as synaptic plasticity and learn ...

EPFL2019

Placement of Virtual Containers on NUMA systems: A Practical and Comprehensive Model

Baptiste Joseph Eustache Lepers

Our work addresses the problem of placement of threads, or virtual cores, onto physical cores in a multicore NUMA system. Different placements result in varying degrees of contention for shared resources, so choosing the right placement can have a large ef ...

USENIX ASSOC2018

A Machine Learning-Based Strategy for Efficient Resource Management of Video Encoding on Heterogeneous MPSoCs

David Atienza Alonso, Marina Zapater Sancho, Arman Iranfar, William Andrew Simon

The design of new streaming systems is becoming a major area of research to deploy services targeted in the Internet-of-Things (IoT) era. In this context, the new High Efficiency Video Coding (HEVC) standard provides high efficiency and scalability of qual ...

2018

Miniphases: Compilation using Modular and Efficient Tree Transformations

Martin Odersky, Dmytro Petrashko

Production compilers commonly perform dozens of transformations on an intermediate representation. Running those transformations in separate passes harms performance. One approach to recover performance is to combine transformations by hand in order to red ...

Assoc Computing Machinery2017

The IX Operating System: Combining Low Latency, High Throughput, and Efficiency in a Protected Dataplan

Edouard Bugnion, Christos Kozyrakis, Georgios Prekas, Mia Primorac

The conventional wisdom is that aggressive networking requirements, such as high packet rates for small messages and μs-scale tail latency, are best addressed outside the kernel, in a user-level networking stack. We present ix, a dataplane operating system ...

Association for Computing Machinery2016

Scaling Up Concurrent Analytical Workloads on Multi-Core Servers

Iraklis Psaroudakis

Today, an ever-increasing number of researchers, businesses, and data scientists collect and analyze massive amounts of data in database systems. The database system needs to process the resulting highly concurrent analytical workloads by exploiting modern ...

EPFL2016

Towards Scalable Synchronization on Multi-Cores

Vasileios Trigonakis

The shift of commodity hardware from single- to multi-core processors in the early 2000s compelled software developers to take advantage of the available parallelism of multi-cores. Unfortunately, only few---so-called embarrassingly parallel---applications ...

EPFL2016

Efficient Communication and Synchronization on Manycore Processors

Darko Petrovic

The increased number of cores integrated on a chip has brought about a number of challenges. Concerns about the scalability of cache coherence protocols have urged both researchers and practitioners to explore alternative programming models, where cache co ...

EPFL2015

Shared Frontend for Manycore Server Processors

Ilknur Cansu Kaynak

Instruction-supplymechanisms, namely the branch predictors and instruction prefetchers, exploit recurring control flow in an application to predict the applicationâ s future control flow and provide the core with a useful instruction stream to execute in ...

EPFL2015