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Concept

Instruction set architecture

Related publications (26)

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic

Giovanni De Micheli, Mathias Soeken, Eleonora Testa

Emerging technologies such as plasmonics and photonics are promising alternatives to CMOS for high throughput applications, thanks to their waveguide's low power consumption and high speed of computation. Besides these qualities, these novel technologies a ...

2020

SpecROP: Speculative Exploitation of ROP Chains

Mathias Josef Payer, Atri Bhattacharyya, Andrés Sánchez Marín

Speculative execution attacks, such as Spectre, reuse code from the victim’s binary to access and leak secret information during speculative execution. Every variant of the attack requires very particular code sequences, necessitating elaborate gadget-sear ...

2020

Boolean satisfiability in quantum compilation

Giovanni De Micheli, Mathias Soeken, Heinz Riener, Bruno Schmitt Antunes, Giulia Meuli, Fereshte Mozafari Ghoraba

Quantum compilation is the task of translating a quantum algorithm implemented in a high-level quantum programming language into a technology-dependent instructions flow for a physical quantum computer. To tackle the large gap between the quantum program a ...

ROYAL SOC2020

Modifying Stride Length in Isolation and in Combination With Foot Progression Angle and Step Width Can Improve Knee Kinetics Related to Osteoarthritis; A Preliminary Study in Healthy Subjects

Brigitte Jolles-Haeberli

The purpose of this study was to determine the effects of modifying stride length (SL) on knee adduction and flexion moments, two markers of knee loading associated with medial-compartment knee osteoarthritis (OA) progression. This study also tested if SL ...

2020

Program compilation for large-scale quantum computers

Giulia Meuli

Practical realizations of quantum computers are poised to deliver outstanding computational capabilities far beyond the reach of any classical supercomputer. While classical systems are reliably implemented using CMOS technology, the fabrication of quantu ...

EPFL2020

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

Yunho Oh

Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To increase the per-warp cache size prior techniques proposed warp throttling which limits the number of active warps. Warp thr ...

ASSOC COMPUTING MACHINERY2019