Concept

Transistor–transistor logic

Related publications (28)

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies

Giovanni De Micheli, Heinz Riener, Akash Kumar

Emerging reconfigurable nanotechnologies allow the implementation of self-dual functions with a fewer number of transistors as compared to traditional CMOS technologies. To achieve better area results for Reconfigurable Field-Effect Transistors (RFET)-base ...

IEEE2021

Active-Device Losses in Resonant Power Converters: A Case Study with Class-E Inverters

Elison de Nazareth Matioli, Remco Franciscus Peter van Erp, Armin Jafari, Palliyage Srilak Nirmana Perera

Recent research has reported an undesirable OFF-state loss in high-frequency soft-switching power converters, such as resonant converters. This loss is attributed to a hysteresis loss related to the charging-discharging process of the output capacitance of ...

IEEE2021

Dimensional scaling of high-speed printed organic transistors enabling high-frequency operation

Vivek Subramanian

Printed electronics has promised to deliver low-cost, large-area and flexible electronics for mass-market applications for some time; however, so far one limiting factor has been device performance. Over the last decade, great progress has been made in ter ...

IOP PUBLISHING LTD2020

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Paolo Ienne, Grace Zgheib, Stefan Nikolic

Technology scaling makes metal delay ever more problematic, but routing between Look-Up Tables (LUTs) still passes through a series of transistors. It seems wise to avoid the corresponding delay whenever possible. Direct connections between LUTs, both with ...

ASSOC COMPUTING MACHINERY2020

A 49 mu W 6th-Order Chebyshev SSF-based Low-Pass Analog Filter for IEEE 802.11ax

Christian Enz, Alessandro Pezzotta, Daniel Mathias Bold

In this paper a continuous-time low-pass analog filter based on the Cascoded Super Source Follower (C-SSF) architecture, implemented in a 28-nm bulk CMOS process, is presented. The target application is the transceiver analog baseband for the next-generati ...

IEEE2020

Write Termination circuits for RRAM : A Holistic Approach From Technology to Application Considerations

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Marco Antonio Rios

While Resistive Random Access Memories (RRAM) are perceived nowadays as a promising solution for the future of computing, these technologies suffer from intrinsic variability regarding programming voltage, switching speed and achieved resistance values. Wr ...

IEEE2020

Characterization and Modeling of Mismatch in Cryo-CMOS

Edoardo Charbon

This paper presents a device matching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 K down to 4 ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic

Giovanni De Micheli, Mathias Soeken, Eleonora Testa

Emerging technologies such as plasmonics and photonics are promising alternatives to CMOS for high throughput applications, thanks to their waveguide's low power consumption and high speed of computation. Besides these qualities, these novel technologies a ...

2020