Mediaspace scheduled maintenance: Aug 25, 2026 07:00 - 12:00 AM. During this time, videos will be temporarily unavailable. Check status updates.

Concept

3D XPoint

Related publications (30)

Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Flavio Ponzina, Marco Antonio Rios

The increasing size of Convolutional Neural Networks (CNNs) and the high computational workload required for inference pose major challenges for their deployment on resource-constrained edge devices. In this paper, we address them by proposing a novel In-M ...

IEEE2021

Write Termination circuits for RRAM : A Holistic Approach From Technology to Application Considerations

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Marco Antonio Rios

While Resistive Random Access Memories (RRAM) are perceived nowadays as a promising solution for the future of computing, these technologies suffer from intrinsic variability regarding programming voltage, switching speed and achieved resistance values. Wr ...

IEEE2020

Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures

David Atienza Alonso, Marina Zapater Sancho, Yasir Mahmood Qureshi

Next generation workloads, such as genome sequencing, have an astounding impact in the healthcare sector. Sequence alignment, the first step in genome sequencing, has experienced recent breakthroughs, which resulted in next generation sequencing (NGS). As ...

2020

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Miguel Peon Quiros, Marco Antonio Rios

Resistive switching memory technologies (RRAM) are seen by most of the scientific community as an enabler for Edge-level applications such as embedded deep Learning, AI or signal processing of audio and video signals. However, going beyond a "simple'' repl ...

IEEE2020

Accurate deep neural network inference using computational phase-change memory

Irem Boybat Kara, Abu Sebastian

In-memory computing using resistive memory devices is a promising non-von Neumann approach for making energy-efficient deep learning inference hardware. However, due to device variability and noise, the network needs to be trained in a specific way so that ...

Nature Research2020

Switching event detection and self-termination programming circuit for energy efficient ReRAM memory arrays

Alexandre Sébastien Julien Levisse

Energy efficiency remains a challenge for the design of non-volatile resistive memories (ReRAMs) arrays. This memory technology suffers from intrinsic variability in switching speed, programming voltages and resistance levels. The programming conditions of ...

2019

Analog Control of Retainable Resistance Multistates in HfO2 Resistive-Switching Random Access Memories (ReRAMs)

Yusuf Leblebici, Jury Sandrini, Elmira Shahrabi, Cecilia Giovinazzo

Resistive-switching random access memory (ReRAM) technologies are nowadays a good candidate to overcome the bottleneck of Von Neumann architectures, taking advantage of their logic-in-memory capability and the ability to mimic biological synapse behavior. ...

AMER CHEMICAL SOC2019

Material and Electrical study of HfO2-Based Resistive Random Access Memories (ReRAMs)

Behnoush Attarimashalkoubeh

Resistive Random Access Memories (ReRAMs) have been researched intensively in the last past decades as a promising alternatives technology for the next-generation non-volatile memory (NVM) devices. ReRAMâ s excellent performance properties such as high sw ...

EPFL2019

Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization

Yusuf Leblebici, Thomas La Grange, Tugba Demirci, Elmira Shahrabi

The integration of the resistive random access memory (ReRAM) with CMOS logic circuitry provides a solution to scaling limitations, and offers promising candidates for use in next generation computing applications. It is challenging to realize a reliable, ...

ELSEVIER SCIENCE BV2019

ReRAM From Material Study to CMOS Co-integration

Elmira Shahrabi

The revolution of information-technology owes to silicon-based complementary-metal-oxide (CMOS) technology. However, CMOS technology approaches its physical limitation hardening the further progress of memory devices as well as computing paradigm requiring ...

EPFL2019

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

David Atienza Alonso, Pierre-Emmanuel Julien Marc Gaillardon, Marina Zapater Sancho, Xifan Tang, Yasir Mahmood Qureshi, Edouard Giacomin

The need for running complex Machine Learning (ML) algorithms, such as Convolutional Neural Networks (CNNs), in edge devices, which are highly constrained in terms of computing power and energy, makes it important to execute such applications efficiently. ...

2019

OneFile: A Wait-free Persistent Transactional Memory

Nachshon Cohen

A persistent transactional memory (PTM) library provides an easy-to-use interface to programmers for using byte-addressable non-volatile memory (NVM). Previously proposed PTMs have, so far, been blocking. We present OneFile, the first wait-free PTM with in ...

IEEE COMPUTER SOC2019

Fine-Grain Checkpointing with In-Cache-Line Logging

James Richard Larus, Nachshon Cohen, David Teksen Aksun

Non-Volatile Memory offers the possibility of implementing high-performance, durable data structures. However, achieving performance comparable to well-designed data structures in non-persistent (transient) memory is difficult, primarily because of the cos ...

ACM2019

Closing the Performance Gap Between Volatile and Persistent Key-Value Stores Using Cross-Referencing Logs

Matej Pavlovic

Key-Value (K-V) stores are an integral building block in modern datacenter applications. With byteaddressable persistent memory (PM) technologies, such as Intel/Micron's 3D XPoint, on the horizon, there has been an influx of new high performance K-V stores ...

USENIX ASSOC2018

An FPGA-Based Test System for RRAM Technology Characterization

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Maxime Victor Thammasack

Resistive random access memory (RRAM) technologies have recently gained large attention from the academic and industrial research communities. Significant efforts have been made to enhance the performance of the memory stacks from both communities through ...

2018

The Inherent Cost of Remembering Consistently

Rachid Guerraoui, Mihail Igor Zablotchi, Nachshon Cohen

Non-volatile memory (NVM) promises fast, byte-addressable and durable storage, with raw access latencies in the same order of magnitude as DRAM. But in order to take advantage of the durability of NVM, programmers need to design persistent objects which ma ...

2018

The Inherent Cost of Remembering Consistently

Rachid Guerraoui, Mihail Igor Zablotchi, Nachshon Cohen

2018

Perspective on training fully connected networks with resistive memories: Device requirements for multiple conductances of varying significance

Giorgio Cristiano, Massimo Giordano

Novel Deep Neural Network (DNN) accelerators based on crossbar arrays of non-volatile memories (NVMs)-such as Phase-Change Memory or Resistive Memory-can implement multiply-accumulate operations in a highly parallelized fashion. In such systems, computatio ...

2018

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Alexandre Sébastien Julien Levisse, Pierre-Emmanuel Julien Marc Gaillardon

With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile memory appears to be more and more costly and technologically challenging. Beyond floating-gate memory technologies, bipolar resistive random access memories ...

2018

Design Guidelines for High-Performance SCM Hierarchies

Babak Falsafi, Edouard Bugnion, Javier Picorel Obando, Alexandros Daglis, Mark Johnathon Sutherland, Dmitrii Ustiugov

With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a fewfactors of DRAM. Nevertheless, the latency-sensitive nature of memory-residen ...

ACM2018