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Concept

Row hammer

Related publications (25)

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Adam Shmuel Teman, Robert Giterman

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher pow ...

MDPI2024

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

Andreas Peter Burg, Robert Giterman, Halil Andac Yigit, Emmanuel Nieto Casarrubias

Gain-cell embedded DRAM (GC-eDRAM) is a high-density logic-compatible alternative to conventional static random-access memory (SRAM) and embedded DRAM (eDRAM). However, GC-eDRAM suffers from a reduced data retention time (DRT) at deeply-scaled process node ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

Quantum error correction using squeezed Schrodinger cat states

Vincenzo Savona, David Schlegel, Fabrizio Minganti

Bosonic quantum codes redundantly encode quantum information in the states of a quantum harmonic oscillator, making it possible to detect and correct errors. Schrodinger cat codes-based on the superposition of two coherent states with opposite displacement ...

AMER PHYSICAL SOC2022

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Robert Giterman

Embedded memories, mostly implemented with static random access memory (SRAM), dominate the area and power of integrated circuits. Gain-cell embedded DRAM (GC-eDRAM) is an alternative to SRAM due to its high density, low power consumption, and two-ported f ...

ELSEVIER SCI LTD2020

Bridging the Latency Gap between NVM and DRAM for Latency-bound Operations

Anastasia Ailamaki, Georgios Psaropoulos

Non-Volatile Memory (NVM) technologies exhibit 4× the read access latency of conventional DRAM. When the working set does not fit in the processor cache, this latency gap between DRAM and NVM leads to more than 2× runtime increase for queries dominated by ...

ACM2019

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Atri Bhattacharyya

When applications have unpredictable memory accesses or irregular control flow, dataflow circuits overcome the limitations of statically scheduled high-level synthesis (HLS). If memory dependences cannot be determined at compile time, dataflow circuits rel ...

IEEE COMPUTER SOC2019

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

Yunho Oh

Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To increase the per-warp cache size prior techniques proposed warp throttling which limits the number of active warps. Warp thr ...

ASSOC COMPUTING MACHINERY2019

Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection

Robert Giterman, Adam Shmuel Teman

A gain-cell embedded DRAM (GC-eDRAM) is an attractive logic-compatible alternative to the conventional static random access memory (SRAM) for the implementation of embedded memories, as it offers higher density, lower leakage, and two-ported operation. How ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Design Guidelines for High-Performance SCM Hierarchies

Babak Falsafi, Edouard Bugnion, Javier Picorel Obando, Alexandros Daglis, Mark Johnathon Sutherland, Dmitrii Ustiugov

With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a fewfactors of DRAM. Nevertheless, the latency-sensitive nature of memory-residen ...

ACM2018

An Accelerator for High Efficient Vision Processing

Paolo Ienne, Robert Fasthuber

In recent years, neural network accelerators have been shown to achieve both high energy efficiency and high performance for a broad application scope within the important category of recognition and mining applications. Still, both the energy efficiency a ...

Ieee-Inst Electrical Electronics Engineers Inc2017

Power-System State Estimation based on PMUs : Static and Dynamic Approaches - from Theory to Real Implementation

Lorenzo Zanni

An increasing number of phasor measurement units (PMUs) are being deployed in power systems in order to enhance the situational awareness and, in the near future, we expect that many networks will be extensively equipped with PMUs. These devices provide ac ...

EPFL2017

Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Pascal Giard

Polar codes are a recently proposed family of provably capacity-achieving error-correction codes that received a lot of attention. While their theoretical properties render them interesting, their practicality compared to other types of codes has not been ...

Ieee2017

A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design

Andreas Peter Burg, Adam Shmuel Teman, Pascal Andreas Meinerzhagen, Robert Giterman

Gain cell embedded DRAM (GC-eDRAM) is a high-density alternative to SRAM for ultra-low-power systems. However, due to its dynamic nature, GC-eDRAM requires power-hungry refresh cycles to ensure data retention. Traditional design approaches dictate configur ...

Ieee2016

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

Andreas Peter Burg, Adam Shmuel Teman, Pascal Andreas Meinerzhagen, Robert Giterman

Logic compatible gain cell (GC) embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, non-ratioed operation, low static leakage, and 2-port functionality. However, traditional GC-eDRAM implementations require boosted c ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories

Andreas Peter Burg, Georgios Karakonstantis, Pascal Andreas Meinerzhagen, Robert Giterman, Adam Shmuel Teman

Current variation aware design methodologies, tuned for worst-case scenarios, are becoming increasingly pessimistic from the perspective of power and performance. A good example of such pessimism is setting the refresh rate of DRAMs according to the worst- ...

2015

Approximate Computing With Unreliable Dynamic Memories

Andreas Peter Burg, Robert Giterman, Georgios Karakonstantis, Adam Shmuel Teman, Shrikanth Ganapathy

Embedded memories account for a large fraction of the overall silicon area and power consumption in modern SoC(s). While embedded memories are typically realized with SRAM, alternative solutions, such as embedded dynamic memories (eDRAM), can provide highe ...

2015

ShiDianNao: shifting vision processing closer to the sensor

Paolo Ienne, Robert Fasthuber

ACM2015

Multi-Gigabyte On-Chip DRAM Caches for Servers

Dorde Jevdic

While DRAM latency has long been recognized as a major bottleneck in servers, DRAM bandwidth is emerging as an important bottleneck as server processors shift to many-core architectures to allow for sustainable throughput improvements. The rapid expansion ...

EPFL2015

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

Andreas Peter Burg, Adam Shmuel Teman, Pascal Andreas Meinerzhagen, Robert Giterman

Gain cells have recently been shown to be a viable alternative to static random access memory in low-power applications due to their low leakage currents and high density. The primary component of power consumption in these arrays is the dynamic power cons ...

Institute of Electrical and Electronics Engineers2014

BuMP: Bulk Memory Access Prediction and Streaming

Babak Falsafi, Boris Robert Grot, Javier Picorel Obando, Stavros Volos

With the end of Dennard scaling, server power has emerged as the limiting factor in the quest for more capable datacenters. Without the benefit of supply voltage scaling, it is essential to lower the energy per operation to improve server efficiency. As th ...

2014