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Related publications (31)

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Access pattern based optimization of memory access

Anastasia Ailamaki, Georgios Psaropoulos

A method for optimizing memory access for database operations is provided. The method may include identifying an access pattern associated with a database operation. The access pattern may include data required to perform the database operation. One or mor ...

2020

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Philip Brisk, Mirjana Stojilovic

RePlAce is a state-of-the-art prototype of a flat, analytic, and nonlinear global cell placement algorithm, which models a placement instance as an electrostatic system with positively charged objects. It can handle large-scale standard-cell and mixed-cell ...

IEEE2020

Understanding Computational Costs of Cellular-Level Brain Tissue Simulations Through Analytical Performance Models

Felix Schürmann, Francesco Cremonesi

Computational modeling and simulation have become essential tools in the quest to better understand the brain's makeup and to decipher the causal interrelations of its components. The breadth of biochemical and biophysical processes and structures in the b ...

HUMANA PRESS INC2020

Accurate deep neural network inference using computational phase-change memory

Irem Boybat Kara, Abu Sebastian

In-memory computing using resistive memory devices is a promising non-von Neumann approach for making energy-efficient deep learning inference hardware. However, due to device variability and noise, the network needs to be trained in a specific way so that ...

Nature Research2020

Real-Time Personalized Atrial Fibrillation Prediction on Multi-Core Wearable Sensors

David Atienza Alonso, Amir Aminifar, Miguel Peon Quiros, Adriana Arza Valdes, Elisabetta De Giovanni

In the recent Internet-of-Things (IoT) era where biomedical applications require continuous monitoring of relevant data, edge computing keeps gaining more and more importance. These new architectures for edge computing include multi-core and parallel compu ...

2021

Functionality Enhanced Memories for Edge-AI Embedded Systems

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Pierre-Emmanuel Julien Marc Gaillardon, Marco Antonio Rios, William Andrew Simon

With the surge in complexity of edge workloads, it appeared in the scientific community that such workloads cannot be anymore overflown to the cloud due to the huge edge device to server communication energy cost and the high energy consumption induced in ...

IEEE2019

DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses

Paolo Ienne, Mikhail Asiatici

The effective bandwidth of the FPGA external memory, usually DRAM, is extremely sensitive to the access pattern. Nonblocking caches that handle thousands of outstanding misses (miss-optimized memory systems) can dynamically improve bandwidth utilization wh ...

IEEE2019

In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA

Paolo Ienne, Mikhail Asiatici, Gabor Andras Csordas

For efficient acceleration on FPGA, it is essential for external memory to match the throughput of the processing pipelines. However, the usable DRAM bandwidth decreases significantly if the access pattern causes frequent row conflicts. Memory controllers ...

IEEE COMPUTER SOC2019

Improving Main-memory Database System Performance through Cooperative Multitasking

Georgios Psaropoulos

Database systems access memory either sequentially or randomly. Contrary to sequential access and despite the extensive efforts of computer architects, compiler writers, and system builders, random access to data larger than the processor cache has been s ...

EPFL2019

HetExchange: Encapsulating heterogeneous CPU-GPU parallelism in JIT compiled engines

Anastasia Ailamaki, Raja Appuswamy, Manolis Karpathiotakis, Periklis Chrysogelos

Modern server hardware is increasingly heterogeneous as hardware accelerators, such as GPUs, are used together with multicore CPUs to meet the computational demands of modern data analytics workloads. Unfortunately, query parallelization techniques used by ...

2019

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

Yunho Oh

Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To increase the per-warp cache size prior techniques proposed warp throttling which limits the number of active warps. Warp thr ...

ASSOC COMPUTING MACHINERY2019