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Concept

Glossary of computer hardware terms

Related publications (16)

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Dataflow programming is a methodology that enables the development of high-level, parametric programs that are independent of the underlying platform. This approach is particularly useful for heterogeneous platforms, as it eliminates the need to rewrite ap ...

SPRINGER2023

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Aurélien François Gilbert Bloch

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

EPFL2023

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Writing and optimizing application software for heterogeneous platforms including GPU units is a very difficult task that requires designer efforts and resources to consider several key elements to obtain good performance. Dataflow programming has shown to ...

2022

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

The performance of programs executed on heterogeneous parallel platforms largely depends on the design choices regarding how to partition the processing on the various different processing units. In other words, it depends on the assumptions and parameters ...

MDPI2022

Atomic object reads for in-memory rack-scale computing

Babak Falsafi, Boris Robert Grot, Alexandros Daglis

A distributed memory system including a plurality of chips, a plurality of nodes that are distributed across the plurality of chips such that each node is comprised within a chip, each node includes a dedicated local memory and a processor core, and each l ...

2018

High Performance Transaction Processing on Non-Uniform Hardware Topologies

Danica Porobic

Transaction processing is a mission critical enterprise application that runs on high-end servers. Traditionally, transaction processing systems have been designed for uniform core-to-core communication latencies. In the past decade, with the emergence of ...

EPFL2016

Robust and Efficient 3D Model of an Electromagnetic Induction (EMI) Sensor

Yves Perriard, Chafic Abu Antoun

Eddy current induction is used in a wide range of electronic devices, for example in detection sensors. Due to the advances in computer hardware and software, the need for 3D computation and system comprehension is a requirement to develop and optimize suc ...

2014

Comparison Framework of FPGA-based GNSS Signals Acquisition Architectures

Pierre-André Farine, Cyril Botteron, Jérôme Leclère

The acquisition of Global Navigation Satellite Systems signals using Code Division Multiple Access can be performed through classical correlation or using a Fourier transform. These methods are well known but what is missing is a comparison of their perfor ...

Institute of Electrical and Electronics Engineers2013

Round-Based Consensus Algorithms, Predicate Implementations and Quantitative Analysis

Fatemeh Borran

Fault-tolerant computing is the art and science of building computer systems that continue to operate normally in the presence of faults. The fault tolerance field covers a wide spectrum of research area ranging from computer hardware to computer software. ...

EPFL2011

Inducing Thermal-Awareness in Multicore Systems Using Networks-on-Chip

David Atienza Alonso

Technology scaling imposes an ever increasing temperature stress on digital circuit design due to transistor density, especially on highly integrated systems, such as Multi- Processor Systems-on-Chip (MPSoCs). Therefore, temperature-aware design is mandato ...

IEEE Computer Society2009

Self-replicating hardware for reliability: The embryonics project

Daniel Mange, Pierre-André Mudry, Joël Rossier

The multicellular structure of biological organisms and the interpretation in each of their cells of a chemical program (the DNA string or genome) is the source of inspiration for the Embryonics (embryonic electronics) project, whose final objective is the ...

2007

A multitasking and data-driven architecture for multi-agents simulations

Sébastien Schertenleib

The expansion of 3D real-time simulations (3DRTS) into millions of homes together with the technical progress of computers hardware force to approach software developments for 3DRTS from different perspectives. From an historical standpoint, 3DRTS started ...

EPFL2006

Self-replication for reliability: bio-inspired hardware and the embryonics project

Daniel Mange, Pierre-André Mudry, Joël Rossier

The growth and operation of all living beings are directed by the interpretation, in each of their cells, of a chemical program, the DNA string or genome. This process is the source of inspiration for the Embryonics (embryonic electronics) project, whose f ...

2006

Routing Aware Switch Hardware Customization for Networks on Chips

Giovanni De Micheli, Srinivasan Murali

Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC wit ...

2006

Multi-unit global energy management and optimization for network-on-chip applications

Zeynep Toprak Deniz

The problem of energy optimization in multi-core systems (such as single-chip multiprocessors) where the individual energy demands of various processing elements are governed by instantaneous workload requirements is well defined in literature. The signifi ...

EPFL2006

TRUSS: A Reliable, Scalable Server Architecture

Babak Falsafi

Traditional reliable servers require costly design changes to the processor, use custom system or application software, or cannot scale beyond a few processing elements. We present TRUSS, a family of server architectures providing reliable, scalable comput ...

2005