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Concept

Bitwise operation

Related publications (22)

EdgeAI-Aware Design of In-Memory Computing Architectures

Marco Antonio Rios

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Flavio Ponzina, Marco Antonio Rios

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional o ...

2023

Programmable Logic Gates Based On Tunable Multistable Mechanisms

Simon Nessim Henein, Ilan Vardi, Hubert Pierre-Marie Benoît Schneegans, Mohamed Gamal Abdelrahman Ahmed Zanaty

Binary logic operations are the building blocks of computing machines. In this paper, we present a new programmable binary logic gate based on programmable multistable mechanisms (PMM), which are multistable structures whose stability behavior depends on m ...

AMER SOC MECHANICAL ENGINEERS2020

Blade: An in-Cache Computing Architecture for Edge Devices

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, William Andrew Simon, Yasir Mahmood Qureshi

Area and power constrained edge devices are increasingly utilized to perform compute intensive workloads, necessitating increasingly area and power efficient accelerators. In this context, in-SRAM computing performs hundreds of parallel operations on spati ...

2020

Structural Rewriting in XOR-Majority Graphs

Giovanni De Micheli, Mathias Soeken

In this paper, we present a structural rewriting method for a recently proposed XOR-Majority graph (XMG), which has exclusive-OR (XOR), majority-of-three (MAJ), and inverters as primitives. XMGs are an extension of Majority-Inverter Graphs (MIGs). Previous ...

ASSOC COMPUTING MACHINERY2019

A Fast, Reliable and Wide-voltage-range In-memory Computing Architecture

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, William Andrew Simon

In-Memory Computing (IMC) solutions, and particularly bitline computing in SRAM, appear promising as they mitigate one of the most energy consuming aspects in computation: data movement. In this work we propose a fast (2.4Ghz for bitwise operations and 2.4 ...

Association for Computing Machinery2019

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

Yunho Oh

Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To increase the per-warp cache size prior techniques proposed warp throttling which limits the number of active warps. Warp thr ...

ASSOC COMPUTING MACHINERY2019

An Ergodic Theory of Binary Operations-Part II: Applications to Polarization

Rajai Nasser

An open problem in polarization theory is to determine the binary operations that always lead to polarization (in the general multilevel sense) when they are used in Arikan style constructions. This paper, which is presented in two parts, solves this probl ...

Institute of Electrical and Electronics Engineers2017

Secure numerical and logical multi party operations

Bin Lu

We derive algorithms for efficient secure numerical and logical operations in the semi-honest model ensuring statistical or perfect security for secure multi-party computation (MPC). To derive our algorithms for trigonometric functions, we use basic mathem ...

Elsevier Science Bv2017

A Compiler for Parallel and Resource-Constrained Programmable in-Memory Computing

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Mathias Soeken, Giulia Meuli

Solid-state resistive switches have recently enabled low-power, scalable, non-volatile memories. Their proven intrinsic logic operation, allowing design of in-memory computing systems, attracted the attention of the research community. A Programmable Logic ...

2017

An Ergodic Theory of Binary Operations-Part I: Key Properties

Rajai Nasser

Ieee-Inst Electrical Electronics Engineers Inc2016

Ergodic Theory Meets Polarization I: A Foundation of Polarization Theory

Rajai Nasser

An open problem in polarization theory is to determine the binary operations that always lead to polarization when they are used in Arıkan style constructions. This paper solves this problem by providing a necessary and sufficient condition for a binary op ...

IEEE2015

Majority logic synthesis

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

A method for optimizing an implementation of a logic circuit, comprising steps of providing an interpretation of the logic circuit in terms of 3 Boolean variable majority operators M, with each of the majority operators being a function of a plurality of v ...

2015

Efficient Recursive Diffusion Layers for Block Ciphers, and Hash Functions

Pouyan Sepehrdad

Many modern block ciphers use maximum distance separable (MDS) matrices as the main part of their diffusion layers. In this paper, we propose a very efficient new class of diffusion layers constructed from several rounds of Feistel-like structures whose ro ...

Springer2015

Biconditional BDD: A Novel Canonical BDD for Logic Synthesis targeting XOR-rich Functions

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

We present a novel class of decision diagrams, called Biconditional Binary Decision Diagrams (BBDDs), that enable efficient logic synthesis for XOR-rich functions. BBDDs are binary decision diagrams where the Shannon’s expansion is replaced by the bicondit ...

2013

Toward one Symbol Network Coding Vectors

Pascal Frossard, Nikolaos Thomos

In this paper, we propose a novel design for network coding vectors that limits the overhead information. Network coding vectors contain information regarding the operations the packets have undergone in the network nodes. They are used at the decoder side ...

Institute of Electrical and Electronics Engineers2012

On-line frequency adaptation and movement imitation for rhythmic robotic tasks

Auke Ijspeert, Tadej Petric

In this paper we present a novel method to obtain the basic frequency of an unknown periodic signal with an arbitrary waveform, which can work online with no additional signal processing or logical operations. The method originates from non-linear dynamica ...

SAGE Publications2011

Architecture of a Real-Time Platform Independant GPS L1 Software Receiver

Personal digital assistants or mobile phones applications are not anymore restricted to multimedia or wireless communications, but have been extended to handle Global Positioning System (GPS) functionalities. Consequently, the growing market of GPS capable ...

EPFL2010

Methodology for the Digital Calibration of Analog Circuits and Systems Using Sub-binary Radix DACs

Maher Kayal, Marc Pastre

This paper presents a methodology for digitally calibrating analog circuits and systems. Based on the detection of an imperfection by a simple comparator, a successive approximations algorithm tunes a compensation current. The latter is generated by a sub- ...

2010

Pre-Synthesis Optimization of Arithmetic Circuits

Ajay Kumar Verma

The efficient synthesis of circuits is a well-studied problem. Due to the NP-hardness of the problem, no optimal algorithm has been presented so far. However, the heuristics presented by several researchers in the past, which are also adopted by commercial ...

EPFL2010