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Concept

Design for testing

Related publications (25)

A Dual-Channel Gate Driver Design with Active Voltage Balancing Circuit for Series Connection of SiC MOSFETs

Drazen Dujic, Rui Wang

Dual-channel gate driver is commonly utilized in the industry for accommodating the widespread use of half-bridge power modules. As wide-bandgap devices become increasingly prevalent due to their superior switching characteristics compared with conventiona ...

2024

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time

Mirjana Stojilovic

Side-channel CPU disassembly is a side-channel attack that allows an adversary to recover instructions executed by a processor. Not only does such an attack compromise code confidentiality, it can also reveal critical information on the system’s internals. ...

IEEE2022

Closing Leaks: Routing Against Crosstalk Side-Channel Attacks

Mirjana Stojilovic, Seyedeh Sharareh Mirzargar

This paper presents an extension to PathFinder FPGA routing algorithm, which enables it to deliver FPGA designs free from risks of crosstalk attacks. Crosstalk side-channel attacks are a real threat in large designs assembled from various IPs, where some I ...

2020

Rethinking Secure FPGAs: Towards a Cryptography-friendly Configurable Cell Architecture and its Automated Design Flow

Edoardo Charbon, Francesco Regazzoni

This work proposes the first fine-grained configurable cell array specifically tailored for the implementation of cryptographic algorithms that can be configured using widely adopted hardware description languages. Our solution can be added as a small, cry ...

IEEE2018

EE3: Quantum engineering: Hype, spin or reality?

Edoardo Charbon

Quantum engineering is an emerging discipline, which involves studies of materials, devices, circuits, and architectures that are necessary to develop quantum-based systems. Recently, quantum computing has received significant attention, and large investme ...

2017

Efficient Hardware Design Of Iterative Stencil Loops

David Atienza Alonso, Ivan Beretta, Alessandro Antonio Nacci

A large number of algorithms for multidimensional signals processing and scientific computation come in the form of iterative stencil loops (ISLs), whose data dependencies span across multiple iterations. Because of their complex inner structure, automatic ...

Ieee-Inst Electrical Electronics Engineers Inc2016

FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages

Nithin George

Field Programmable Gate Arrays (FPGAs) have the unique ability to be configured into application-specific architectures that are well suited to specific computing problems. This enables them to achieve performances and energy efficiencies that outclass oth ...

EPFL2016

Substrate Current Optimization in Smart Power ICs

Pietro Buccella

Safety requirements for modern automotive electronics call for more and more robust power integrated circuits. The mixed-signal IC design flow alone is often no longer capable of tracking possible design failures in complex Smart Power integrated circuits ...

EPFL2016

Ultra Low Noise CMOS Image Sensors

Assim Boukhayma

CMOS Image Sensors (CIS) overtook the charge coupled devices (CCDs) in low noise performance. Photoelectron counting capability is the next step for CIS for ultimate low light performance and new imaging paradigms. This work presents a review of CMOS image ...

EPFL2016

FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction

Paolo Ienne, David Novo Bruna, Barbara Jobstmann, Andrew James Becker, Mohsen A A Ewaida

Functional verification occupies a significant amount of the digital circuit design cycle. In this paper, we present a novel approach to improve circuit debugging which not only localizes errors with high confidence, but can also provide semantically-meani ...

Springer2015

System Design Automation: Challenges and Limitations

Joseph Sifakis

Electronic design automation (EDA) has enabled the integrated circuit industry to sustain exponentially increasing product complexity growth until today, while maintaining consistent product development timeline and costs. We argue that the success of EDA- ...

Ieee-Inst Electrical Electronics Engineers Inc2015

New Data Structures and Algorithms for Logic Synthesis and Verification

Luca Gaetano Amarù

The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The continuous downscaling of CMOS Field Effec ...

EPFL2015

A Circuit Synthesis Flow for Controllable-Polarity Transistors

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

Double-Gate (DG) controllable-polarity Field-Effect Transistors (FETs) are devices whose n- or p- polarity is on-line configurable by adjusting the second gate voltage. Such emerging transistors have been fabricated in silicon nanowires, carbon nanotuges a ...

Institute of Electrical and Electronics Engineers2014

Nanowire systems: technology and design (invited paper)

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Davide Sacchetto, Luca Gaetano Amarù, Michele De Marchi, Shashi Kanth Bobba

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this work, we consider double independent gate, vertically-stacked nanowire FETs with gate-all-around structures and typical diameter of 20-nm. These devices, which we hav ...

Royal Soc2014

Cell Transformations and Physical Design Techniques for 3D Monolithic Integrated Circuits

Giovanni De Micheli, Shashi Kanth Bobba

3D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. In 3DMI technology the 3D contacts, connecting different active layers, are in the order of few 100 nm. Given the advantage of ...

2013

A High-Level Synthesis Flow for the Implementation of Iterative Stencil Loop Algorithms on FPGA Devices

David Atienza Alonso, Ivan Beretta, Alessandro Antonio Nacci

The automatic generation of hardware implementations for a given algorithm is generally a difficult task, especially when data dependencies span across multiple iterations such as in iterative stencil loops (ISLs). In this paper, we introduce an automatic ...

IEEE/ACM Press2013

Compressive Image Acquisition in Modern CMOS IC Design

Yusuf Leblebici, Pierre Vandergheynst, Alexandre Schmid, Mahdad Hosseini Kamal, Nikola Katic

Compressive Sampling (CS) offers bandwidth, power and memory size reduction compared to conventional (Nyquist) sampling. However, very few Integrated Circuit (IC) designs based on CS exist due to the missing link between the well-established CS theory on o ...

Wiley-Blackwell2013

Column-Separated Compressive Sampling Scheme for Low Power CMOS Image Sensors

Yusuf Leblebici, Pierre Vandergheynst, Alexandre Schmid, Mahdad Hosseini Kamal, Nikola Katic, Mustafa Kilic

A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The scheme utilizes an identical pseudo-random sequence for every image column, therefore reducing in-pixel hardware complexity and allowing measurement ...

IEEE2013

Power-Efficient CMOS Image Acquisition System based on Compressive Sampling

Yusuf Leblebici, Pierre Vandergheynst, Alexandre Schmid, Mahdad Hosseini Kamal, Nikola Katic, Mustafa Kilic

A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The prototype design is implemented in a 0.18um standard CMOS technology and utilizes compressed acquisition to boost the overall power efficiency. Spec ...

IEEE2013