Motorola 68000

EVA: An Encrypted Vector Arithmetic Language and Compiler for Efficient Homomorphic Computation

Fully-Homomorphic Encryption (FHE) offers powerful capabilities by enabling secure offloading of both storage and computation, and recent innovations in schemes and implementations have made it all the more attractive. At the same time, FHE is notoriously ...

ASSOC COMPUTING MACHINERY2020

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

Yusuf Leblebici, Davide Sacchetto, Clemens Benedict Nyffeler, Seniz Esra Küçük

In this work, a chip-level post-CMOS processing protocol for 3D integration is presented to achieve multilayer stacking. This protocol includes TSV formation on the top chip, bonding the chips on top of each other, and finally the electrical connection pro ...

2014

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

Yusuf Leblebici, Carlotta Guiducci, Yüksel Temiz

This paper presents a chip-level postcomplementary metal oxide semiconductor (CMOS) processing technique for 3-D integration and through-silicon-via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

Yusuf Leblebici, Alessandro Cevrero, Michail Zervas, Yüksel Temiz, Giulia Beanato, Panagiotis Athanasopoulos, Paolo Giovannini

An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by through-silicon-vias (TSVs). Each die features four 32-bit embedded processors and associated m ...

2012

Ambipolar silicon nanowire FETs with stenciled sub-µm metal gate

Giovanni De Micheli, Yusuf Leblebici, Jürgen Brugger, Andreea Veronica Savu, Davide Sacchetto

A fully CMOS compatible fabrication flow using low temperature a-Si LPCVD and stencil lithography has been developed and proved suitable for SiNW FinFETs having ambipolar conductance. The stencil mask has been demonstrated to be a real option for sub-micro ...

2010

New functionality and ultra low power: key opportunities for post-CMOS era

Mihai Adrian Ionescu

This paper addresses the challenges and opportunities offered by post-CMOS devices in terms of new functionality and ultra low power. It focuses on the illustration of: (i) the quest for the new electronic abrupt switches (tunnel-FET and IMOS/PIMOS) and (i ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008

Full wafer integration of NEMS on CMOS by nanostencil lithography

Jürgen Brugger, Marc Antonius Friedrich van den Boogaart

Wafer scale nanostencil lithography is used to define 200 nm scale mechanically resonating silicon cantilevers monolithically integrated into CMOS circuits. We demonstrate the simultaneous patterning of ~2000 nanodevices by post-processing standard CMOS wa ...

2006

A hybrid CMOS-SET co-fabrication platform using nano-grain polysilicon wires

Mihai Adrian Ionescu, Didier Bouvet, Vincent Pott, Santanu Mahapatra, Serge Ecoffey

This paper presents a process for the co-fabrication of self-aligned NMOS and single electron transistors made by gated polysilicon wires. The realization of SET–MOS hybrid architectures is also reported. The proposed process exploits an original low energ ...

2005

Processor Enhancements for Media Streaming Applications

Pierre Vandergheynst, Eric Debes, Sébastien Bilavarn

The development of more processing demanding applications on the Internet (video broadcasting) on one hand and the popularity of recent devices at the user level (digital cameras, wireless videophones, ...) on the other hand introduce challenges at several ...

Springer, Kluwer Academic Publishers2005