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Concept

Word (computer architecture)

Related publications (23)

Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads

David Atienza Alonso, Marina Zapater Sancho, Darong Huang, Luis Maria Costero Valero, Qunyou Liu

The increasing demand for computing power and the emergence of heterogeneous computing architectures have driven the exploration of innovative techniques to address current limitations in both the compute and memory subsystems. One such solution is the use ...

2024

Preconditioning techniques for generalized Sylvester matrix equations

Yannis Dirk Voet

Sylvester matrix equations are ubiquitous in scientific computing. However, few solution techniques exist for their generalized multiterm version, as they now arise in an increasingly large number of applications. In this work, we consider algebraic parame ...

2023

2D Nanosystems: Applications of 2D Semiconductors for In-Memory Computing

Guilherme Migliato Marega

Machine learning and data processing algorithms have been thriving in finding ways of processing and classifying information by exploiting the hidden trends of large datasets. Although these emerging computational methods have become successful in today's ...

EPFL2023

Real-Time Nonlinear Model Predictive Control for Fast Mechatronic Systems

Petr Listov

This thesis presents an efficient and extensible numerical software framework for real-time model-based control. We are motivated by complex and challenging mechatronic applications spanning from flight control of fixed-wing aircraft and thrust vector cont ...

EPFL2022

Full key recovery side-channel attack against ephemeral SIKE on the Cortex-M4

Aymeric Genet, Novak Kaluderovic

This paper describes the first practical single-trace side-channel power analysis of SIKE. While SIKE is a post-quantum key exchange, the scheme still relies on a secret elliptic curve scalar multiplication which involves a loop of a double-and-add procedu ...

2021

Optimization Methods for Control: From Embedded Programmable Hardware to Data-Driven Process Optimization

Harsh Ambarishkumar Shukla

The research community has been making significant progress in hardware implementation, numerical computing and algorithm development for optimization-based control. However, there are two key challenges that still have to be overcome for optimization-base ...

EPFL2021

Exploiting Errors for Efficiency: A Survey from Circuits to Applications

Babak Falsafi, Alexandros Daglis, Dorde Jevdic, Eva Darulova, Mattia Cacciotti

When a computational task tolerates a relaxation of its specification or when an algorithm tolerates the effects of noise in its execution, hardware, system software, and programming language compilers or their runtime systems can trade deviations from cor ...

ASSOC COMPUTING MACHINERY2020

Hierarchical Control in Islanded DC Microgrids With Flexible Structures

Giancarlo Ferrari Trecate, Pulkit Nahata

Hierarchical architectures stacking primary, secondary, and tertiary layers are widely employed for the operation and control of islanded dc microgrids (dcmGs) composed of distribution generation units (DGUs), loads, and power lines. However, a comprehensi ...

2020

Speculative Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

With FPGAs facing broader application domains, the conversion of imperative languages into dataflow circuits has been recently revamped as a way to overcome the conservatism of statically scheduled high-level synthesis. Apart from the ability to extract pa ...

ASSOC COMPUTING MACHINERY2019

CoreNEURON : An Optimized Compute Engine for the NEURON Simulator

Felix Schürmann, James Gonzalo King, Pramod Shivaji Kumbhar, Fabien Jonathan Delalondre, Aleksandr Ovcharenko, Jérémy Pierre Benoit Fouriaux

The NEURON simulator has been developed over the past three decades and is widely used by neuroscientists to model the electrical activity of neuronal networks. Large network simulation projects using NEURON have supercomputer allocations that individually ...

2019

Storage method and apparatus for random access memory using codeword storage

Harm Cronie

A memory circuit, such as an embedded DRAM array, stores information as groups of bits or data using information coding in storage and retrieval data, instead of each bit being stored separately. Write data words can be mapped to storage format words that ...

2016

Faster ECC over $\mathbb{F}_{2^{521}-1}$

Robert Granger

In this paper we present a new multiplication algorithm for residues modulo the Mersenne prime

2^{521}−1

. Using this approach, on an Intel Haswell Core i7-4770, constant-time variable-base scalar multiplication on NIST’s (and SECG’s) curve P-521 requires ...

Springer Berlin Heidelberg2015

GPU Acceleration for Simulating Massively Parallel Many-Core Platforms

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

Emerging massively parallel architectures such as a general-purpose processor plus many-core programmable accelerators are creating an increasing demand for novel methods to perform their architectural simulation. Most state-of-the-art simulation technolog ...

Institute of Electrical and Electronics Engineers2015

A sieve algorithm based on overlattices

In this paper, we present a heuristic algorithm for solving exact, as well as approximate, shortest vector and closest vector problems on lattices. The algorithm can be seen as a modified sieving algorithm for which the vectors of the intermediate sets lie ...

Cambridge Univ Press2014

GIPSY: Joining Spatial Datasets with Contrasting Density

Anastasia Ailamaki, Thomas Heinis, Farhan Tauheed, Mirjana Pavlovic

Many scientific and geographical applications rely on the efficient execution of spatial joins. Past research has produced several efficient spatial join approaches and while each of them can join two datasets, the problem of efficiently joining two datase ...

2013

Verification of STM on relaxed memory models

Rachid Guerraoui

Software transactional memories (STM) are described in the literature with assumptions of sequentially consistent program execution and atomicity of high level operations like read, write, and abort. However, in a realistic setting, processors use relaxed ...

Springer Verlag2011

High-Performance Modular Multiplication on the Cell Processor

Joppe Willem Bos

This paper presents software implementation speed records for modular multiplication arithmetic on the synergistic processing elements of the Cell broadband engine (Cell) architecture. The focus is on moduli which are of special interest in elliptic curve ...

Springer2010

Software Transactional Memory on Relaxed Memory Models

Rachid Guerraoui

Pseudo-code descriptions of STMs assume sequentially consistent program execution and atomicity of high-level STM operations like read, write, and commit. These assumptions are often violated in realistic settings, as STM implementations run on relaxed mem ...

Springer2009

A Fast Parallel Matrix Multiplication Reconfigurable Unit Utilized In Face Recognitions Systems

In this paper we present a reconfigurable device which significantly improves the execution time of the most computational intensive functions of three of the most widely used face recognition algorithms; those tasks multiply very large dense matrices. The ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Bit Precision Analysis for Compressed Sensing

Mohammad Amin Shokrollahi, Mahdi Cheraghchi Bashi Astaneh

This paper studies the stability of some reconstruction algorithms for compressed sensing in terms of the bit precision. Considering the fact that practical digital systems deal with discretized signals, we motivate the importance of the total number of ac ...

2009

Related publications (23)

2^{521}−1

. Using this approach, on an Intel Haswell Core i7-4770, constant-time variable-base scalar multiplication on NIST’s (and SECG’s) curve P-521 requires ...

Springer Berlin Heidelberg2015