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Concept

Hyper-threading

Related publications (24)

Boosting Efficiency of External Pipelines by Blurring Application Boundaries

Anastasia Ailamaki, Periklis Chrysogelos, Anna Patricia Herlihy

Modern application development addresses increasingly specialized problems using domain-specific utilities, such as Optical Code Recognition and standalone statistical tools. The diversity of tooling, combined with the ever-growing volume of data, requires ...

2022

Architecture Exploration and Optimization of Heterogeneous Many-Core Compute and Memory Architectures with Architectural Extensions

Yasir Mahmood Qureshi

The expeditious proliferation of Internet connectivity and the growing adoption of digital products have transformed various spheres of our everyday lives. This increased digitization of society has led to the emergence of new applications, which are deplo ...

EPFL2021

Thread-Placement Learning

Rachid Guerraoui, Vasileios Trigonakis, Karolos Antoniadis

In a non-uniform memory access machine, the placement of software threads to hardware cores can have a significant effect on the performance of concurrent applications. Detecting the best possible placement for each application is a necessity for thread sc ...

IEEE COMPUTER SOC2020

Gyrokinetic simulations on many- and multi-core architectures with the global electromagnetic Particle-In-Cell Code ORB5

Laurent Villard, Stephan Brunner, Emmanuel Lanti, Noé Thomas Elie Ohana, Claudio Gheller

Gyrokinetic codes in plasma physics need outstanding computational resources to solve increasingly complex problems, requiring the effective exploitation of cutting-edge HPC architectures. This paper focuses on the enabling of ORB5, a state-of-the-art, fir ...

2021

Biomolecular Simulation: a Perspective from High Performance Computing

Ursula Röthlisberger, Viacheslav Bolnykh

High-Performance Computing is impacting on all biomedical sciences, including molecular biophysics. Here, we describe general parallel computing strategies (multi-threading and distributed computing) used in all the natural sciences, including molecular bi ...

WILEY-V C H VERLAG GMBH2020

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Philip Brisk, Mirjana Stojilovic

RePlAce is a state-of-the-art prototype of a flat, analytic, and nonlinear global cell placement algorithm, which models a placement instance as an electrostatic system with positively charged objects. It can handle large-scale standard-cell and mixed-cell ...

IEEE2020

Duality in the Mechanism of Hexagonal ZnO/CuxO Nanowires Inducing Sulfamethazine Degradation under Solar or Visible Light

César Pulgarin, Juan Kiwi, Sami Rtimi

This study presents the first evidence for the photocatalytic performance of ZnO/CuxO hexagonal nanowires leading to sulfamethazine (SMT) degradation. The chemical composition of the nanowires was determined by X-ray fluorescence (XRF). The sample with the ...

2019

SMoTherSpectre: Exploiting Speculative Execution through Port Contention

Babak Falsafi, Mathias Josef Payer, Atri Bhattacharyya

Spectre, Meltdown, and related attacks have demonstrated that kernels, hypervisors, trusted execution environments, and browsers are prone to information disclosure through micro-architectural weaknesses. However, it remains unclear as to what extent other ...

ACM2019

Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

Boris Robert Grot, Siddharth Gupta

In a drive to maximize resource utilization, today's datacenters are moving to colocation of latency-sensitive and batch workloads on the same server. State-of-the-art deployments, such as those at Google, colocate such diverse workloads even on a single S ...

IEEE2019

Improving Main-memory Database System Performance through Cooperative Multitasking

Georgios Psaropoulos

Database systems access memory either sequentially or randomly. Contrary to sequential access and despite the extensive efforts of computer architects, compiler writers, and system builders, random access to data larger than the processor cache has been s ...

EPFL2019

Fast Energy Estimation Through Partial Execution of HPC Applications

Marina Zapater Sancho, José Luis Ayala Rodrigo

In order to optimize the energy use of servers in Data Centers, techniques such as power capping or power budgeting are usually deployed. These techniques rely on the prediction of the power and execution time of applications. These data are obtained via d ...

IEEE2018

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

Philip Brisk, Mirjana Stojilovic

This paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallefization strategies: (1) routing multiple nets in parallel; and (2) routing one net at a time, while parallelizing the ...

IEEE2018

USSR: An UltraSound Sparse Regularization framework

Jean-Philippe Thiran, Yves Wiaux, Adrien Georges Jean Besson, Dimitris Perdios, Marcel Arditi, Florian Martinez

Ultrafast ultrasound (US) imaging uses unfocused waves to insonify the whole medium of interest at once, allowing pulse-echo US imaging to achieve very high frame rates, at the cost of a lower image quality. In this paper, we present USSR, an UltraSound Sp ...

Ieee2017

Virtualized Execution Runtime for FPGA Accelerators in the Cloud

Paolo Ienne, Mikhail Asiatici, Nithin George

FPGAs offer high performance coupled with energy efficiency making them extremely attractive computational resources within a cloud ecosystem. However, to achieve this integration and make them easy to program, we first need to enable users with varying ex ...

2017

FloDB: Unlocking Memory in Persistent Key-Value Stores

Rachid Guerraoui, Mihail Igor Zablotchi, Vasileios Trigonakis, Oana Maria Balmau

Log-structured merge (LSM) data stores enable to store and process large volumes of data while maintaining good performance. They mitigate the I/O bottleneck by absorbing updates in a memory layer and transferring them to the disk layer in sequential batch ...

2017

A Scala Library for Testing Student Assignments on Concurrent Programming

Mikaël Mayer, Ravichandhran Kandhadai Madhavan

We present a lightweight library for testing concurrent Scala programs by systematically exploring multiple interleavings between user-specified operations on shared objects. Our library is targeted at beginners of concurrent programming in Scala, runs on ...

Assoc Computing Machinery2016

Automated Classification of Data Races Under Both Strong and Weak Memory Models

George Candea, Cristian Zamfir, Baris Can Cengiz Kasikci

Data races are one of the main causes of concurrency problems in multithreaded programs. Whether all data races are bad, or some are harmful and others are harmless, is still the subject of vigorous scientific debate [Narayanasamy et al. 2007; Boehm 2012]. ...

Assoc Computing Machinery2015

GPU Acceleration for Simulating Massively Parallel Many-Core Platforms

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

Emerging massively parallel architectures such as a general-purpose processor plus many-core programmable accelerators are creating an increasing demand for novel methods to perform their architectural simulation. Most state-of-the-art simulation technolog ...

Institute of Electrical and Electronics Engineers2015

Transactions Chasing Scalability and Instruction Locality on Multicores

Pinar Tözün

For several decades, online transaction processing (OLTP) has been one of the main server applications that drives innovations in the data management ecosystem, and in turn the database and computer architecture communities. Recent hardware trends oblige s ...

EPFL2014

Data Races vs. Data Race Bugs: Telling the Difference with Portend

George Candea, Cristian Zamfir, Baris Can Cengiz Kasikci

Even though most data races are harmless, the harmful ones are at the heart of some of the worst concurrency bugs. Alas, spotting just the harmful data races in programs is like finding a needle in a haystack: 76%-90% of the true data races reported by sta ...

Acm Order Department, P O Box 64145, Baltimore, Md 21264 Usa2012