James Richard LarusExpertise
James Larus is a Professor Emeritus and former Dean of the School of Computer and Communication Sciences (IC) at EPFL (école Polytechnique Fédérale de Lausanne). Before joining IC in October 2013, Larus was a researcher, manager, and director in Microsoft Research for over 16 years and an Assistant and Associate Professor in the Computer Sciences Department at the University of Wisconsin, Madison.Larus has been an active contributor to numerous communities. He published over 100 papers (with 14 be
Pejman Lotfi KamranTeaching & PhD Courses Advanced multiprocessor architecture CS-471 Multiprocessors are basic building blocks for all computer systems. This course covers the architecture and organization of modern multiprocessors, prevalent accelerators (e.g., GPU, TPU), and datacenters. It includes a research project on multiprocessors and post-Moore era datacenters. Parallelism and concurrency in software CS-302 From sensors,to smart phones,to the world's largest datacenters and supercompu
Emmanuel LantiTeaching & PhD Courses Parallel programming PHYS-743 Learn the concepts, tools and API's that are needed to debug, test, optimize and parallelize a scientific application on a cluster from an existing code or from scratch. Both OpenMP (shared memory) and MPI (distributed memory) paradigms are presented and experimented.
David Atienza AlonsoDavid Atienza Alonso is an associate professor of EE and director of the Embedded Systems Laboratory (ESL) at EPFL, Switzerland. He received his MSc and PhD degrees in computer science and engineering from UCM, Spain, and IMEC, Belgium, in 2001 and 2005, respectively. His research interests include system-level design methodologies for multi-processor system-on-chip (MPSoC) servers and edge AI architectures. Dr. Atienza has co-authored more than 350 papers, one book, and 12 patents in these previous areas. He has also received several recognitions and award, among them, the ICCAD 10-Year Retrospective Most Influential Paper Award in 2020, Design Automation Conference (DAC) Under-40 Innovators Award in 2018, the IEEE TCCPS Mid-Career Award in 2018, an ERC Consolidator Grant in 2016, the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award in 2012, and a Faculty Award from Sun Labs at Oracle in 2011. He has also earned two best paper awards at the VLSI-SoC 2009 and CST-HPCS 2012 conference, and five best paper award nominations at the DAC 2013, DATE 2013, WEHA-HPCS 2010, ICCAD 2006, and DAC 2004 conferences. He serves or has served as associate editor of IEEE Trans. on Computers (TC), IEEE Design & Test of Computers (D&T), IEEE Trans. on CAD (T-CAD), IEEE Transactions on Sustainable Computing (T-SUSC), and Elsevier Integration. He was the Technical Program Chair of DATE 2015 and General Chair of DATE 2017. He served as President of IEEE CEDA in the period 2018-2019 and was GOLD member of the Board of Governors of IEEE CASS from 2010 to 2012. He is a Distinguished Member of ACM and an IEEE Fellow.
Giovanni De MicheliExpertise
Design technologies for integrated systems on silicon, such as synthesis, hw/sw codesign and low-power design, as well as systems on heterogeneous platforms including electrical and biological components.
Scientific Director of EcoCloud Center at EPFL
Directing activities towards creating sustainable computation including AI.Designing energy-savvy data centers and edge devices.
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Please read http://si2.epfl.ch/~demichel/
Giovanni De Micheli is a research scientist in electronics and Stephan BrunnerTeaching & PhD PhD Students Hugo Jean Elie Chkroun, Nicole Vadot, Oraz Anuaruly, Haomin Sun, Isabel Muzio, Fabien Nicolas Jeanquartier Past EPFL PhD Students Ajay Chandrarajan Jayalekshmi, Arnas Volcokas Past EPFL PhD Students as codirector Xavier Lapillonne, Thibaut Vernay, Julien Stanislas Pierre Dominski, Gabriele Merlo, Emmanuel Lanti, Noé Ohana, Moahan Murugappan Courses Plasma instabilities PHYS-736 To complete the theoretical knowledge acquired before the graduate studies.
Paolo IennePaolo Ienne has been a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, he worked for the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG) where he was at the head of the Embedded Memories unit in the Design Libraries division. His research interests include various aspects of computer and processor architecture, FPGAs and reconfigurable computing, electronic design automation, and computer arithmetic. Ienne was a recipient of Best Paper Awards at the 20th, 24th, and 28th ACM/SIGDA International Symposia on Field-Programmable Gate Arrays (FPGA), in 2012, 2016 and 2020, at the 19th and 30th International Conference on Field-Programmable Logic and Applications (FPL), in 2009 and 2020, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), in 2007, and at the 40th Design Automation Conference (DAC), in 2003; many other papers have been candidates to Best Paper Awards in prestigious venues. He has served as general, programme, and topic chair of renown international conferences, including organizing in Lausanne the 26th International Conference on Field-Programmable Logic and Applications (FPL) in 2016. He serves on the steering committee of the IEEE Symposium on Computer Arithmetic (ARITH) and of the International Conference on Field-Programmable Logic and Applications (FPL). Ienne has guest edited a number of special issues and special sections on various topics for IEEE and ACM journals. He is regularly member of program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. He has been an associate editor of ACM Transactions on Architecture and Code Optimization (TACO), since 2015, of ACM Computing Surveys (CSUR), since 2014, and of ACM Transactions on Design Automation of Electronic Systems (TODAES) from 2011 to 2016.
Marco MattavelliTeaching & PhD Past EPFL PhD Students Christophe Clerc, Ruohua Zhou, Beilu Shao, Christophe Lucarz, Richard Thavot, Ab Al Hadi Bin Ab Rahman, Endri Bezati, Simone Casale Brunet, Malgorzata Michalska, Ana Angelica Hernandez Lopez, Aurélien Bloch, Mustafa Besirli, Ünsal Öztürk Past EPFL PhD Students as codirector Sylvain Aguirre Courses Systems and architectures for signal processing EE-555 Study of the essential components and implementation technologies of digital signal processing and commu
Pasquale Davide SchiavoneTeaching & PhD Courses Design technologies for integrated systems CS-472 Hardware compilation is the process of transforming specialized hardware description languages into circuit descriptions, which are iteratively refined, detailed and optimized. The course presents algorithms, tools and methods for hardware compilation and logic synthesis.
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