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Concept

Microarchitecture

Related publications (31)

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

Paolo Ienne, Mikhail Asiatici

FPGAs rely on massive datapath parallelism to accelerate applications even with a low clock frequency. However, applications such as sparse linear algebra and graph analytics have their throughput limited by irregular accesses to external memory for which ...

ASSOC COMPUTING MACHINERY2019

Exploiting Flow Graph of System of ODEs to Accelerate the Simulation of Biologically-Detailed Neural Networks

Felix Schürmann, Bruno Ricardo Da Cunha Magalhães

Exposing parallelism in scientific applications has become a core requirement for efficiently running on modern distributed multicore SIMD compute architectures. The granularity of parallelism that can be attained is a key determinant for the achievable ac ...

IEEE2019

Parallel integro-differential equation solving via multi-channel reciprocal bianisotropic metasurface augmented by normal susceptibilities

Karim Achouri, Ali Momeni

Analog optical signal processing has dramatically transcended the speed and energy limitations accompanied with its digital microelectronic counterparts. Motivated by recent metasurface?s evolution, the angular scattering diversity of a reciprocal passive ...

2019

High Speed SAR ADC Architectures in 28nm FDSOI CMOS

Mustafa Kilic

The demand on high speed Analog to Digital Converters (ADCs) has increased considerably the last years. From communications circuit to high speed oscilloscopes, Giga Samples per second (GS/s) ADCs are requested. With the scaling of the CMOS technology, des ...

EPFL2019

Distributed Logless Atomic Durability with Persistent Memory

Babak Falsafi, Alexandros Daglis, Siddharth Gupta

Datacenter operators have started deploying Persistent Memory (PM), leveraging its combination of fast access and persistence for significant performance gains. A key challenge for PM-aware software is to maintain high performance while achieving atomic du ...

2019

A 512 x 512 SPAD Image Sensor With Integrated Gating for Widefield FLIM

Edoardo Charbon, Claudio Bruschini, Arin Can Ülkü, Ivan Michel Antolovic

In this paper, we report on SwissSPAD2, an image sensor with 512 x 512 photon-counting pixels, each comprising a single-photon avalanche diode (SPAD), a 1-b memory, and a gating mechanism capable of turning the SPAD ON and OFF, with a skew of 250 and 344 p ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

HetExchange: Encapsulating heterogeneous CPU-GPU parallelism in JIT compiled engines

Anastasia Ailamaki, Raja Appuswamy, Manolis Karpathiotakis, Periklis Chrysogelos

Modern server hardware is increasingly heterogeneous as hardware accelerators, such as GPUs, are used together with multicore CPUs to meet the computational demands of modern data analytics workloads. Unfortunately, query parallelization techniques used by ...

2019

Low-Overhead Dynamic Instruction Mix Generation using Hybrid Basic Block Profiling

Willy Zwaenepoel, Andrzej Pawel Nowak

Dynamic instruction mixes form an important part of the toolkits of performance tuners, compiler writers, and CPU architects. Instruction mixes are traditionally generated using software instrumentation, an accurate yet slow method, that is normally limite ...

2018

Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers

Cunxi Yu

The paper presents a novel method to verify and debug gate-level arithmetic circuits implemented in Galois Field arithmetic. The method is based on forward reduction of the specification polynomials of the circuit in GF(2(m)) using GF(2) models of its logi ...

IEEE2018

LTRF: Enabling High-Capacity Register Files for GPUs via Hardware/Software Cooperative Register Prefetching

Babak Falsafi, Mario Paulo Drumond Lages De Oliveira, Hamid Sarbazi-Azad

Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bottleneck for future GPUs due to long access latency, high power consumption, ...

2018

Fat Caches For Scale-Out Servers

Babak Falsafi, Boris Robert Grot, Stavros Volos, Dorde Jevdic

The authors propose a high-capacity cache architecture that leverages emerging high-bandwidth memory modules. High-capacity caches capture the secondary data working sets of scale-out workloads while uncovering significant spatiotemporal locality across da ...

Institute of Electrical and Electronics Engineers2017